An Open-Source High-Level Graphical Signal Processing Language with Simulation and HDL Generation

TL;DR

The paper addresses the reliance of the CASPER toolflow on proprietary MATLAB/Simulink frontends, which creates compatibility and openness barriers. It proposes an open-source Scilab frontend that uses Xcos to model CASPER Yellow/Green blocks, generating HDL-backed DSP IP cores and the necessary artifacts ($jasper.json$, $jasper.per$) to drive the existing backend. A spectrometer demonstration on an RFSoC4x2 validates that the Scilab-based toolflow reproduces core CASPER functionality while offering a backend architecture adaptable to other frontends (e.g., GNU Radio). The work advances open collaboration in radio astronomy instrument design by enabling HDL-based frontend generation and HDL-native simulation, reducing dependence on proprietary software.

Abstract

The CASPER (Collaboration for Astronomy Signal Processing and Electronic Research) toolflow is a widely used framework for designing and implementing digital signal processing systems, particularly in the field of radio astronomy. It provides a set of tools and libraries that enable researchers to create custom hardware and software solutions for processing astronomical data. The CASPER toolflow has been instrumental in the development of Field-Programmable Gate Array (FPGA) based digital instruments for various radio telescopes, enabling for real-time data processing and analysis. However, the current frontend tool that CASPER uses for high-level FPGA design is based on Model Composer integrated into MATLAB/Simulink, which is a proprietary software. In this paper, we introduce Scilab as a new frontend tool for the CASPER toolflow. Scilab is an open-source software platform for numerical computation and data visualization, which offers a similar environment to MATLAB/Simulink for designing CASPER blocks, generating FPGA Intellectual Property (IP) cores, and simulating Digital Signal Processing (DSP) systems. We present our implementation of Scilab in the CASPER toolflow and demonstrate its capabilities by developing an FPGA based spectrometer on a RFSoC4x2, a commonly used CASPER platform well suited to radio astronomy applications. We have also developed Scilab support for other CASPER compatible platforms. Our results show that Scilab can successfully be used as an alternate frontend for CASPER-based designs.

Figures (25)

• Figure 1: AMD Gateway In and Gateway Out blocks in Simulink. These could be multi-bit buses or single-bit lines, which depend on the design.
• Figure 2: AMD Xilinx HDL Blockset in Simulink. (More AMD Xilinx basic blocks are found in the Simulink AMD library.)
• Figure 3: A CASPER example Simulink design targeting an RFSoC4x2 FPGA board. In this design, four snapshot blocks capture data from an RFDC (ADC) block. A software register and an edge detect block are used to enable/disable the data capture.
• Figure 4: The generation of the $jasper.per$ file, which contains the configuration data of the Yellow blocks and the IP core information.
• Figure 5: The main process of the generation of gogogo.tcl and top.v in Python:(1) Python scripts parse the $jasper.per$, and generate the peripherals objects based on the Yellow blocks information; (2) top module is created based on the peripherals objects; (3) Check for any Yellow blocks marked with a non-None value of the "template_project" attribute; (4) Generate constraints for different Yellow blocks; (5) Check if the constraints are valid.