TLC-Plan: A Two-Level Codebook Based Network for End-to-End Vector Floorplan Generation

TL;DR

TLC-Plan tackles the problem of end-to-end vector floorplan generation from input boundaries, addressing the limitations of raster-to-vector pipelines and handcrafted graph methods. It introduces a hierarchical two-level VQ-VAE that encodes global room layouts and local room polygons into discrete codes, unified by a CodeTree. An autoregressive transformer samples CodeTrees conditioned on the boundary to produce CAD-ready vector floorplans without explicit topology priors. Empirical results on RPLAN and LIFULL show state-of-the-art fidelity and geometric accuracy, with strong layout diversity and robust generalization, demonstrating the method’s practical potential for constraint-aware architectural design.

Abstract

Automated floorplan generation aims to improve design quality, architectural efficiency, and sustainability by jointly modeling global spatial organization and precise geometric detail. However, existing approaches operate in raster space and rely on post hoc vectorization, which introduces structural inconsistencies and hinders end-to-end learning. Motivated by compositional spatial reasoning, we propose TLC-Plan, a hierarchical generative model that directly synthesizes vector floorplans from input boundaries, aligning with human architectural workflows based on modular and reusable patterns. TLC-Plan employs a two-level VQ-VAE to encode global layouts as semantically labeled room bounding boxes and to refine local geometries using polygon-level codes. This hierarchy is unified in a CodeTree representation, while an autoregressive transformer samples codes conditioned on the boundary to generate diverse and topologically valid designs, without requiring explicit room topology or dimensional priors. Extensive experiments show state-of-the-art performance on RPLAN dataset (FID = 1.84, MSE = 2.06) and leading results on LIFULL dataset. The proposed framework advances constraint-aware and scalable vector floorplan generation for real-world architectural applications. Source code and trained models are released at https://github.com/rosolose/TLC-PLAN.

Figures (15)

• Figure 1: TLC-Plan directly generates vector floorplans end-to-end in two stages: (a) an input boundary with front-door location, (b) a layout-level codebook predicts semantically labeled room bounding boxes, and (c) a polygon-level codebook refines each box into a detailed room polygon. The resulting floorplan is geometrically aligned and CAD-ready, requiring no post-processing.
• Figure 2: Hierarchical two-level representation: the layout level captures global room bounding boxes, while the polygon level refines them into detailed shapes, enabling structured codebook learning.
• Figure 3: Network architecture for codebook learning: layout-level and polygon-level models share the same architecture but differ in input tokenization. The encoder extracts sequence features, which are quantized via a learned codebook, and the decoder reconstructs masked inputs from quantized codes to capture reusable design patterns.
• Figure 4: CodeTree-based vector floorplan generation: (a) given an input boundary, the model encodes boundary features, autoregressively predicts a CodeTree, and decodes it into room polygons; (b) the CodeTree Generator encodes the layout, boundary, and room polygons, quantizes them with learned codebooks, and concatenates them into a unified CodeTree for supervision and generation.
• Figure 5: Geometric metrics for vector-based boundary constraints. Given an input boundary polygon (white) and generated room polygons (green and red), we measure Gap (uncovered interior area), Overlap (intersecting area between rooms), and Exceed (area extending beyond the boundary).