A Multiscale Workflow for Thermal Analysis of 3DI Chip Stacks

TL;DR

The paper tackles the problem of thermally analyzing 2.5D/3D HI stacks with detailed BEOL structures, where fast, accurate simulations are hindered by multiscale geometry. It introduces a multiscale workflow that couples die-scale FEM with RVE-based homogenization to yield a spatially varying anisotropic BEOL conductivity tensor, extracted from GDSII/OASIS data via a static-condensation approach and integrated into standard FEM solvers like MuMFiM. Key contributions include automated RVE generation (2×2 μm RVEs across 4.3 μm BEOL, 5,105 RVEs), a robust conductivity extraction method, and demonstration on a chip-scale geometry showing BEOL heterogeneity and its impact on heat flow. This approach enables accurate, BEOL-aware, die-scale thermal analysis suitable for rapid design iterations in 3DIC packaging, ultimately aiding thermal-aware integration decisions.

Abstract

Thermally aware design of 2.5D and 3D advanced packaging systems will require fast, accurate, and powerful thermal analysis of chiplets, stacks, and packages. These systems contain multiple materials with non-linear heat transfer properties and geometric feature sizes that span many orders of magnitude. The smallest heterostructures in the front and back ends of the line present significant thermal modeling and analysis challenges in isolation. Replicated millions or billions of times in a chiplet stack, these structures present a near insurmountable hurdle to meeting the speed and accuracy needed of analysis in the design process. Additionally, establishing precise parameter values for the materials in these systems, when size and temperature dependencies create significant deviations from bulk properties, further complicates the problem. To address these issues, we have developed a multiscale methodology that advances the current state of the field by enabling die-scale simulations that capture phenomena arising from the structural details of the BEOL metallization stack. Taking advantage of the large length-scale separation between the BEOL features and the die-level structures, we employ a hierarchical, multiscale, finite-element approach. This hierarchical method uses a standard finite element method (FEM) formulation on a die or package scale, using computational homogenization to obtain effective thermal conductivities in the BEOL. Referring to industry-standard layout and design files, we construct and solve a locally appropriate subscale FEM problem in a representative volume element (RVE) at every quadrature point in the macroscale FEM problem. To accomplish this, RVE models are automatically constructed, meshed, and used to compute homogenized, anisotropic, thermal conductivities from the relevant GDSII or OASIS.

Figures (7)

• Figure 1: Front view of the proxy-chip modeled in this paper. In the multiscale model, the BEOL properties are extracted from a test vehicle. A heat flux with integrated power of 1.256 mW is applied to the bottom surface. The top surface is exposed to an ambient temperature of 40$\circ$ C with a convection coefficient, $h$, of 4.0 W/K mm2. All dimensions are reported in $\upmu$m. The red dashed line (T-T) and purple dashed line (B-B) represent the top and bottom of the BEOL, respectively, where the temperature fields are reported. In the text, these surfaces are referred to as top surface and bottom surface respectively.
• Figure 2: In panel a, the front view of the macroscale model is shown with a highly graded tetrahedral mesh to minimize the total number of elements in regions far away from the thin BEOL and FEOL layers. Panel b shows the mesh on the bottom surface of the chip stack (c.f., Fig. \ref{['fig:model-chip']}, surface B-B).
• Figure 3: A schematic of the heat flux on the bottom surface (100$\times$100 $\upmu$m) is shown, where flux is applied to the regions with hash marks. In both cases, a power input flux of 1.256 mW/mm2 is applied. In the uniform case (a) the heat flux is applied uniformly across the bottom surface. In the non-uniform case (b) the heat flux is applied in circular domains on the bottom surface representing the contact patches of microbumps.
• Figure 4: Eleven layers of metal components in exemplar RVEs (five layers of lines and six layers of vias). Dielectric layers have been excluded from the figure so that the metal structures with high conductivity are visible. Dielectrics are included in the multiscale simulation. The RVE in each panel is extracted from different locations in the test vehicle.
• Figure 5: Homogenized BEOL thermal conductivities in the 100$\times$100 $\upmu$m cross-section. We see large spatial heterogeneity that will impact chip-scale hotspot locations. The in-plane components are shown in panel a ($\kappa_{xx}$) and b ($\kappa_{yy}$). The out-of-plane conductivity, $\kappa_{zz}$, is shown in panel c. Maximum off-diagonal terms of the conductivity tensor are four orders of magnitude smaller than diagonal terms ($\kappa_{yz}\sim \kappa_{xz} \sim \kappa_{xy} \sim1.5\times 10^{-4}$ W/m-K). They are not shown as they will have a negligible impact on the heat flow.