Hybrid Coupling Topology with Dynamic ZZ Suppression for Optimizing Circuit Depth during Runtime in Superconducting Quantum Processor

TL;DR

This work addresses the need for higher qubit connectivity with suppressed ZZ cross-talk in superconducting processors to reduce circuit depth. It introduces a hybrid coupling topology where four fixed-frequency transmons connect via a single flux-tunable coupler, with off-resonant Stark drives enabling tunable ZZ interactions. The approach demonstrates a tunable ZZ strength, achieving a maximum around $\\zeta_{max}/2\\pi \\approx 18$ MHz and a substantial swing up to about $\\Delta\\zeta \\approx 30$ MHz, while showing minimal sensitivity at zero-crossing phases. Benchmarking against IBM's Heavy-Hex topology via a Qiskit-based Grover's algorithm test indicates an approximate 20% reduction in circuit depth for higher qubit counts, highlighting the potential for scalable, low-footprint quantum processors.

Abstract

To reduce circuit depth when executing Quantum algorithms, it is necessary to maximize qubit connectivity on a near-term quantum processor. While addressing this, we also need to ensure high gate fidelity, suppression of unwanted ZZ cross-talk, a compact layout footprint, and minimal control hardware complexity to support scalability. In current superconducting quantum chips, fixed coupling is used as it is easier to scale, but it is limited by unwanted static ZZ interaction during single qubit operations, which degrades system performance. To overcome these challenges, we have introduced a first-of-its-kind hybrid tunable-coupling architecture that connects four fixed-frequency transmon qubits using a single coupler. This hybrid coupler uses off-resonant Stark drives to tune ZZ strength between qubit pairs. Experimentally backed simulation results indicate that our proposed hybrid design maximizes the qubit connectivity while reducing control overhead. This design achieves a near 20% reduction in circuit depth compared to IBM's Heavy-Hexagonal layout, showing its potential for scalability.

Figures (8)

• Figure 1: Circuit schematic of the $Q_1-Q_c-Q_2$ coupling architecture. The diagram illustrates the fundamental building block of the proposed processor, consisting of two computational transmon qubits ($Q_1$ and $Q_2$) capacitively coupled to a central flux-tunable transmon coupler ($Q_c$).
• Figure 2: The proposed hybrid coupling topology for maximizing processor scalability. By utilizing the $Q_1$--$Q_c$--$Q_2$ architecture from Fig. 1 as a fundamental unit cell, the system is expanded into a 2D lattice. The blue squares denote fixed-frequency computational transmon qubits ($Q_1$ to $Q_4$), while the pink circles denote flux-tunable transmon couplers ($Q_c$). The interleaved geometry provides high connectivity, where each computational qubit is capacitively coupled to $Q_c$.
• Figure 3: $ZZ$ vs relative drive phase($\Phi_d$) via $Q_c$ (Fig [1]). $\zeta$ is characterized as a function of $\Phi_d$ between off-resonant Stark drives (Fixed amplitude) applied to $Q_1$ and $Q_2$. $Q_c$'s frequency is tuned via external magnetic flux.
• Figure 4: Multi-qubit $ZZ$ interaction for the proposed hybrid coupling topology. $\zeta_d$ is plotted against $\Phi_d$ for four distinct qubit pairs ($Q_1-Q_2$, $Q_3-Q_4$, $Q_1-Q_3$, $Q_2-Q_4$ when $Q_c$'s first transition ($|0> to |1>$) frequency is tuned to 6.2 GHz
• Figure 5: Connectivity matrix analysis of the interaction landscape within the hybrid coupling topology (shown in Fig 6) to capture peak $|\zeta_d|$ for any given pair at fixed off-resonant Stark drive amplitude (when $Q_c$ is tuned to 6.2 GHz