Characterizing Quantum Error Correction Performance of Radiation-induced Errors

TL;DR

This work addresses radiation-induced correlated errors in superconducting quantum error correction by coupling a quasiparticle-density model to a quantum error channel and testing it on a 17-qubit rotated surface code. The authors build a per-cycle, quasi-equilibrium noise model from Geant4/G4CMP-generated generation terms $g_{qp}(t)$ to obtain $x_{qp}(t)$ and update $T_1$ and $T_2$ via $1/T_1$ and $\Gamma_\phi$, ultimately simulating QEC performance with both GAD and Pauli-twirled GAD channels. A new metric, $\zeta_c$, quantifies the mitigation efficacy of radiation-induced errors across chip designs and decoders; results show that phonon downconversion with Cu backside can substantially reduce correlated errors, with only thin Cu layers providing most of the benefit and spacing playing a critical role. The framework is generalizable to arbitrary codes and radiation sources and points toward design optimization, including potential machine-learning–driven surrogates, to efficiently navigate large design spaces. This work thus provides a practical pathway to predict and mitigate radiation-induced QEC failures in superconducting qubits.

Abstract

Radiation impacts are a current challenge with computing on superconducting-based quantum devices because they can lead to widespread correlated errors across the device. Such errors can be problematic for quantum error correction (QEC) codes, which are generally designed to correct independent errors. To address this, we have developed a computational model to simulate the effects of radiation impacts on QEC performance. This is achieved by building from recently developed models of quasiparticle density, mapping radiation-induced qubit error rates onto a quantum error channel and simulation of a simple surface code. We also provide a performance metric to quantify the resilience of a QEC code to radiation impacts. Additionally, we sweep various parameters of chip design to test mitigation strategies for improved QEC performance. Our model approach is holistic, allowing for modular performance testing of error mitigation strategies and chip and code designs.

Figures (5)

• Figure 1: (a) The normalized quasiparticle density $x_{qp}$ for a 17-qubit QPU following a muon strike. These curves are generated using the Geant4/G4CMP simulation and ODE as described in Ref. Yelton2024 and App. \ref{['app:QPM']}. The corresponding QPU design and muon strike location are shown in the inset. The device is modeled with Nb/Al superconducting material platform fabricated on $10\times10\times0.525$ mm$^3$ Si die. No Cu is modeled on the flipside of the chip. (inset) The QPU layout for the rotated [[9,1,3]]] surface code: 17 qubits are arranged into nine data (red), four $X$-parity (blue), and four $Z$-parity (green) ancilla qubits for syndrome readout. The stabilizer plaquettes are shaded as blue and green squares and triangles to help visualize which qubits are checked by which stabilizer measurements. (b) The circuit diagram for the stabilizer rounds consisting of Hadamard (H) and controlled not (CX) gates. The qubit registers are labeled in accordance to those in (a). At the end of the stabilizer rounds, the syndromes are measured out to the classical register. The syndrome measurement projects the data into a quiescent state Cleland2022, which can be saved for future use before the data readout.
• Figure 2: A comparison of the surface code simulation results using the Python packages (a) Qiskit and (b) Stim. The Qiskit simulation uses the GAD channel of Eq. \ref{['eq:GAD']}, while the Stim simulation uses the PTGAD channel for respective noise models. In both cases, $T_1=100$$\mu$s and $T_2=200$$\mu$s for each qubit, and the circuit is sampled 4096 times. In the Qiskit case, the syndrome measurement cycles are chained together by passing the state between sequential rounds. For the Uncorrected curves, no error correction is applied, and $p_L$ is measured from the data parity. For Corrected curves, the historical syndrome data are decoded by a repetition MWPM decoder (see App. \ref{['app:decoder']}), and appropriate bitflips are applied to the $Z$-basis data post measurement. For comparison, the individual rounds are also modeled with single-shot circuit execution, decoding, and correction to calculate the logical error per round $\varepsilon_i$. In this latter scenario, states have no dependence on neighboring cycles. The corresponding $p_L(\varepsilon_i)$ can be calculated using Eq. \ref{['eq:pL']}. Notably, this method overestimates the error compared to state-chained simulations.
• Figure 3: (a) The [[9,1,3]] surface code logical error probability $p_L$ following a muon strike. The simulation consists of the $10\times10$-mm$^2$ chip configuration shown in Figure \ref{['fig:circuit']}(a) with corresponding muon strike location. Average $T_1$ and $T_2$ values are calculated from a 100 muon ensemble as described in Appendix \ref{['app:cufigs']}. To test the efficacy of phonon downconversion, the chip is modeled with Cu of varying thicknesses covering the underside, such as in Iaia2022 and Yelton2024. (b) The performance gap as a function of Cu thickness and qubit spacing. To sweep qubit spacing, the diagram of Figure \ref{['fig:circuit']}(a) is scaled by either a factor of 2 or 4. The chip size is increased to $20\times20$ mm$^2$ and $40\times40$ mm$^2$, while the qubit nearest neighbor spacing is increased from 1 mm to 2 mm and 4 mm. The performance gap $\zeta_c$ is measured over an average of 64 muon strikes normal to the chip surface. (inset) Demonstration of how the performance gap is calculated (shaded region). The difference between $p_L(\mu)$ and $p_L(\bar{\mu})$ is integrated then normalized by the total number of simulated cycles ($N_c\approx1500$).
• Figure 4: $2T_1\Gamma_\phi$ measures the comparison between the dephasing and relaxation rates as a function of $x_{qp}$. The minimum and maximum range of $x_{qp}$ covers the ranges observed in the simulation data. These values have been calculated using the transmon parameters listed in Table \ref{['tab:transmon_params']}.
• Figure 5: Sample $p_L$ curves for the (a) $20\times20$ mm$^2$ and (b) $40\times 40$ mm$^2$ chips. For both devices, the qubits are arranged identically to Figure \ref{['fig:circuit']}(a) inset but are scaled by a respective factor of two or four. Likewise, the muon strike location is also scaled from (1.7, 1.7) mm in Figure \ref{['fig:circuit']}(a) inset to (3.4, 3.4) mm and (6.4, 6.4) mm. For both cases, as Cu metal thickness increases, the $p_L(\mu)$curves start to approach the $p_L(\bar{\mu})$ curve, and $\zeta_c$ approaches zero.