Quantum Sequential Circuits
D. -S. Wang
TL;DR
This work addresses the need for memory and temporal control in quantum computing by introducing quantum sequential circuits (QSCs) built from quantum transistors that store gates as Choi states and operate them via bulk measurements. It proposes a hardware framework that uses ebits and symmetry-protected topological edge modes to realize looped gate activation, enabling a quantum von Neumann-like architecture. The paper develops a complete set of circuit elements, algorithmic modules, and higher-level programming constructs, including quantum control, QFT, QPE, amplitude amplification, gradient descent, and quantum simulation, all within a modular, hybrid hardware model. By integrating quantum programming via superchannels and quantum error-correcting strategies in a matrix-product-state/convolutional-code setting, it outlines a path toward scalable, memory-rich quantum processors that complement conventional qubit-based approaches.
Abstract
This work introduces and characterizes quantum sequential circuits (QSCs) as a hardware-oriented paradigm for quantum computing, built upon a novel foundational element termed the quantum transistor. Unlike conventional qubit-based architectures, QSCs employ symmetry-protected topological junctions where quantum gates are encoded as Choi states via channel-state duality and activated through bulk measurements, utilizing ebits to realize the functional analog of feedback loops in classical sequential circuits. This framework establishes a universal model for quantum computation that inherently incorporates memory and temporal sequencing, complementing existing combinational quantum circuit model. Our work advances the conceptual bridge towards a quantum von Neumann architecture, underscoring the potential of hybrid and modular design principles for the development of large-scale, integrated quantum information processors.
