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COFFEE: A Carbon-Modeling and Optimization Framework for HZO-based FeFET eNVMs

Hongbang Wu, Xuesi Chen, Shubham Jadhav, Amit Lal, Lillian Pentecost, Udit Gupta

TL;DR

The paper tackles the environmental impact of on-chip memories by introducing COFFEE, a cross-stack framework that models both embodied carbon from HZO FeFET fabrication and operational carbon during use. It leverages real fabrication recipes and ACT4 CMOS baselines to quantify embodied emissions, and uses NVMExplorer to assess runtime energy and performance, enabling end-to-end life-cycle carbon analysis. Key findings show that FeFETs can lower carbon footprints per unit memory capacity compared to SRAM (about 4.3× lower per MB), while FE-layer deposition can add up to ~20% of total embodied carbon and up to 11% more CPA in some cases; case studies demonstrate substantial carbon reductions when integrating FeFETs into edge accelerators. The work provides practical insights for sustainable memory design and releases open-source tooling to guide future hardware decisions toward lower life-cycle emissions.

Abstract

Information and communication technologies account for a growing portion of global environmental impacts. While emerging technologies, such as emerging non-volatile memories (eNVM), offer a promising solution to energy efficient computing, their end-to-end footprint is not well understood. Understanding the environmental impact of hardware systems over their life cycle is the first step to realizing sustainable computing. This work conducts a detailed study of one example eNVM device: hafnium-zirconium-oxide (HZO)-based ferroelectric field-effect transistors (FeFETs). We present COFFEE, the first carbon modeling framework for HZO-based FeFET eNVMs across life cycle, from hardware manufacturing (embodied carbon) to use (operational carbon). COFFEE builds on data gathered from a real semiconductor fab and device fabrication recipes to estimate embodied carbon, and architecture level eNVM design space exploration tools to quantify use-phase performance and energy. Our evaluation shows that, at 2 MB capacity, the embodied carbon per unit area overhead of HZO-FeFETs can be up to 11% higher than the CMOS baseline, while the embodied carbon per MB remains consistently about 4.3x lower than SRAM across different memory capacity. A further case study applies COFFEE to an edge ML accelerator, showing that replacing the SRAM-based weight buffer with HZO-based FeFET eNVMs reduces embodied carbon by 42.3% and operational carbon by up to 70%.

COFFEE: A Carbon-Modeling and Optimization Framework for HZO-based FeFET eNVMs

TL;DR

The paper tackles the environmental impact of on-chip memories by introducing COFFEE, a cross-stack framework that models both embodied carbon from HZO FeFET fabrication and operational carbon during use. It leverages real fabrication recipes and ACT4 CMOS baselines to quantify embodied emissions, and uses NVMExplorer to assess runtime energy and performance, enabling end-to-end life-cycle carbon analysis. Key findings show that FeFETs can lower carbon footprints per unit memory capacity compared to SRAM (about 4.3× lower per MB), while FE-layer deposition can add up to ~20% of total embodied carbon and up to 11% more CPA in some cases; case studies demonstrate substantial carbon reductions when integrating FeFETs into edge accelerators. The work provides practical insights for sustainable memory design and releases open-source tooling to guide future hardware decisions toward lower life-cycle emissions.

Abstract

Information and communication technologies account for a growing portion of global environmental impacts. While emerging technologies, such as emerging non-volatile memories (eNVM), offer a promising solution to energy efficient computing, their end-to-end footprint is not well understood. Understanding the environmental impact of hardware systems over their life cycle is the first step to realizing sustainable computing. This work conducts a detailed study of one example eNVM device: hafnium-zirconium-oxide (HZO)-based ferroelectric field-effect transistors (FeFETs). We present COFFEE, the first carbon modeling framework for HZO-based FeFET eNVMs across life cycle, from hardware manufacturing (embodied carbon) to use (operational carbon). COFFEE builds on data gathered from a real semiconductor fab and device fabrication recipes to estimate embodied carbon, and architecture level eNVM design space exploration tools to quantify use-phase performance and energy. Our evaluation shows that, at 2 MB capacity, the embodied carbon per unit area overhead of HZO-FeFETs can be up to 11% higher than the CMOS baseline, while the embodied carbon per MB remains consistently about 4.3x lower than SRAM across different memory capacity. A further case study applies COFFEE to an edge ML accelerator, showing that replacing the SRAM-based weight buffer with HZO-based FeFET eNVMs reduces embodied carbon by 42.3% and operational carbon by up to 70%.
Paper Structure (22 sections, 9 equations, 9 figures, 2 tables)

This paper contains 22 sections, 9 equations, 9 figures, 2 tables.

Figures (9)

  • Figure 1: COFFEE framework encompasses both embodied carbon and operational carbon. The embodied carbon from FeFET fabrication is partitioned into a CMOS baseline, evaluated using ACT 4, and a FeFET-specific component leveraging real manufacturing recipes that provide tool energy and tool time. The operational carbon is obtained from performance and power evaluation using NVMExplorer NVMExplorer. Together, the two stages capture both manufacturing and execution, providing a life cycle analysis on the carbon footprint for FeFET.
  • Figure 2: Take HZO FeFET as an example, the manufacturing steps can be divided into two parts. One is the traditional CMOS baseline, marked by blue color, the other is FEOL special steps to deposit a ferroelectric layer and (optionally) an interfacial layer, bounded by red outline. 25.
  • Figure 3: Diagram of carbon calculation in the proposed COFFEE framework. Source inputs (green) include manufacturing recipe and recent published device configurations 21222324252627. Pink blocks represent carbon categories. Yellow blocks denote the integrated embodied carbon tools and lifetime analysis, while gray boxes NVMExplorer indicate carbon-related attributes integrated in existing tools.
  • Figure 4: The ALD process is divided into four stages: pre-heat, stabilization, HZO deposition, and Al$_2$O$_3$ deposition. For a 20 nm HZO layer and a 3 nm Al$_2$O$_3$ layer, the total process time reaches 17529 s.
  • Figure 5: Power consumption of fabrication equipment, including the chamber, pump, and other modules. The left plot shows the equipment power during the heating stage ($P_{\mathrm{preheat}}$) with uncertainty distribution carboniccad. The right plot shows the equipment power during steady operation at 200$\,^{\circ}\mathrm{C}$ ($P_{\mathrm{steady}}$).
  • ...and 4 more figures