A-Graph: A Unified Graph Representation for At-Will Simulation across System Stacks

TL;DR

This work introduces Architecture-Graph (A-Graph), a unified, cross-stack graph representation that encapsulates application, software, architecture, and circuit events to enable at-will simulation across technologies. The Archx framework provides a user-friendly front-end and scope-based metric retrieval, facilitating automated design-point sweeps under constraints and enabling explainable analysis at any granularity. Through CMOS and superconducting case studies (including FFT, Systolic arrays, neuromorphic computing, FIR, and CNN workloads), Archx demonstrates high accuracy relative to full EDA flows while delivering substantial speedups for design space exploration. Overall, A-Graph and Archx offer a technology- and application-agnostic foundation for fast, cross-stack performance and cost evaluation with enhanced programmability and explainability.

Abstract

As computer systems continue to diversify across technologies, architectures, applications, and beyond, the relevant design space has become larger and more complex. Given such trends, design space exploration (DSE) at early stages is critical to ensure agile development towards optimal performance and cost. Industry-grade EDA tools directly take in RTL code and report accurate results, but do not perform DSE. Recent works have attempted to explore the design space via simulation. However, most of these works are domain-specific and constrain the space that users are allowed to explore, offering limited flexibility between technologies, architecture, and applications. Moreover, they often demand high domain expertise to ensure high accuracy. To enable simulation that is agnostic to technology, architecture, and application at any granularity, we introduce Architecture-Graph (Agraph), a graph that unifies the system representation surrounding any arbitrary application, software, architecture, and circuit. Such a unified representation distinguishes Agraph from prior works, which focus on a single stack, allowing users to freely explore the design space across system stacks. To fully unleash the potential of Agraph, we further present Archx, a framework that implements Agraph. Archx is user-friendly in two ways. First, Archx has an easy-to-use programming interface to automatically generate and sweep design points under user constraints, boosting the programmability. Second, Archx adopts scope-based metric retrieval to analyze and understand each design point at any user-preferred hierarchy, enhancing the explainability. We conduct case studies that demonstrate Agraph's generalization across technologies, architecture, and applications with high simulation accuracy. Overall, we argue that Agraph and Archx serve as a foundation to simulate both performance and cost at will.

Figures (12)

• Figure 1: Overview of A-Graph.
• Figure 2: Patterns of metric aggregation in A-Graph. Circles represent events, while squares represent modules. The top row illustrates the functionality of each aggregation type, while the bottom row provides an example, with the final value shown in green. Module aggregation sums module-level metrics. Summation aggregation propagates metrics upward to the root event, multiplying along edges and summing at the end (+). Specified aggregation distinguishes between sequential (S) and parallel (P) events: sequential aggregation behaves like summation, while parallel aggregation multiplies along edges but computes the maximum at each node.
• Figure 3: Overview of Archx.
• Figure 4: Archx constraint graph and description generation. Nodes represent workload or module parameters, while edges denote constraints. Red edges indicate condition constraints, and purple edges indicate new non-condition constraints after splitting condition constraints in red.
• Figure 5: A-Graph generation