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Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security

Anh Kiet Pham, Van Truong Vo, Vu Trung Duong Le, Tuan Hai Vu, Hoai Luan Pham, Van Tinh Nguyen, Yasuhiko Nakashima

TL;DR

Crypto-RV targets secure IoT/edge environments by delivering a unified, high-performance RISC-V cryptographic co-processor that accelerates a broad set of primitives (SHA-256/512, SHA3-256, SM3, SHAKE-128/256, AES-128, HARAKA-256/512) on a single $64$-bit datapath. It achieves this with three innovations: a high-bandwidth $128\times 64$-bit internal buffer to minimize memory traffic, three cryptography-specialized four-stage pipelines sharing resources, and a double-buffering data-scheduling scheme for continuous big-hash processing. Implemented on a Xilinx ZCU102 FPGA at $160$ MHz, Crypto-RV delivers up to $1{,}061$-fold speedups over baseline RISC-V cores and up to $187.08$ Mbps/W energy efficiency, using about $34{,}704$ LUTs, $37{,}329$ FFs, and $22$ BRAMs. These results demonstrate the viability of high-throughput cryptographic processing in IoT/edge devices and point toward post-quantum extension (e.g., SPHINCS+).

Abstract

Cryptographic operations are critical for securing IoT, edge computing, and autonomous systems. However, current RISC-V platforms lack efficient hardware support for comprehensive cryptographic algorithm families and post-quantum cryptography. This paper presents Crypto-RV, a RISC-V co-processor architecture that unifies support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256 AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. Crypto-RV introduces three key architectural innovations: a high-bandwidth internal buffer (128x64-bit), cryptography-specialized execution units with four-stage pipelined datapaths, and a double-buffering mechanism with adaptive scheduling optimized for large-hash. Implemented on Xilinx ZCU102 FPGA at 160 MHz with 0.851 W dynamic power, Crypto-RV achieves 165 times to 1,061 times speedup over baseline RISC-V cores, 5.8 times to 17.4 times better energy efficiency compared to powerful CPUs. The design occupies only 34,704 LUTs, 37,329 FFs, and 22 BRAMs demonstrating viability for high-performance, energy-efficient cryptographic processing in resource-constrained IoT environments.

Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security

TL;DR

Crypto-RV targets secure IoT/edge environments by delivering a unified, high-performance RISC-V cryptographic co-processor that accelerates a broad set of primitives (SHA-256/512, SHA3-256, SM3, SHAKE-128/256, AES-128, HARAKA-256/512) on a single -bit datapath. It achieves this with three innovations: a high-bandwidth -bit internal buffer to minimize memory traffic, three cryptography-specialized four-stage pipelines sharing resources, and a double-buffering data-scheduling scheme for continuous big-hash processing. Implemented on a Xilinx ZCU102 FPGA at MHz, Crypto-RV delivers up to -fold speedups over baseline RISC-V cores and up to Mbps/W energy efficiency, using about LUTs, FFs, and BRAMs. These results demonstrate the viability of high-throughput cryptographic processing in IoT/edge devices and point toward post-quantum extension (e.g., SPHINCS+).

Abstract

Cryptographic operations are critical for securing IoT, edge computing, and autonomous systems. However, current RISC-V platforms lack efficient hardware support for comprehensive cryptographic algorithm families and post-quantum cryptography. This paper presents Crypto-RV, a RISC-V co-processor architecture that unifies support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256 AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. Crypto-RV introduces three key architectural innovations: a high-bandwidth internal buffer (128x64-bit), cryptography-specialized execution units with four-stage pipelined datapaths, and a double-buffering mechanism with adaptive scheduling optimized for large-hash. Implemented on Xilinx ZCU102 FPGA at 160 MHz with 0.851 W dynamic power, Crypto-RV achieves 165 times to 1,061 times speedup over baseline RISC-V cores, 5.8 times to 17.4 times better energy efficiency compared to powerful CPUs. The design occupies only 34,704 LUTs, 37,329 FFs, and 22 BRAMs demonstrating viability for high-performance, energy-efficient cryptographic processing in resource-constrained IoT environments.
Paper Structure (14 sections, 6 figures, 2 tables)

This paper contains 14 sections, 6 figures, 2 tables.

Table of Contents

  1. INTRODUCTION
  2. PROPOSED CRYPTOGRAPHY RISC-V CO-PROCESSOR
  3. System Architecture and Implementation Platform
  4. Internal buffer for High performance
  5. Cryptography Specialized Unit
  6. Unified SM3/SHA-256/SHA-512 Unit
  7. Unified AES-128/Haraka-256/Haraka-512 Unit
  8. Unified SHA3-256/SHAKE-128/SHAKE-256 Unit
  9. Double-Buffering for Continuous Big-Hash Processing
  10. VERIFICATION AND EVALUATION RESULTS
  11. Verification and Implementation Results on FPGA
  12. Comparison with state-of-the-art CPUs
  13. Comparison with related RISC-V work
  14. CONCLUSION

Figures (6)

  • Figure 1: Overview Crypto-RV Architecture on ZCU102 FPGA SoC
  • Figure 2: Propose (a) Unified SM3/SHA-256/SHA-512 Unit, (b) Unified AES-128/Haraka-256/Haraka-512 Unit
  • Figure 3: Unified SHA3-256/SHAKE-128/SHAKE-256 Unit.
  • Figure 4: Double-buffering schedule.
  • Figure 5: Total cycles per algorithm: Crypto-RV vs RISC-V baseline.
  • ...and 1 more figures