Restoring Sparsity in Potts Machines via Mean-Field Constraints

TL;DR

Constraint-induced density limits the scalability of probabilistic Ising machines. The authors introduce hardware-native p-dits to absorb local constraints into multi-state nodes and mean-field constraints (MFC) to replace dense global couplings with a dynamic bias in a hybrid probabilistic-classical framework, enabling scalable constrained optimization. In the Potts/graph-partitioning setting, H = H_min + λ H_bal with H_min = -∑ J_{ij} δ(s_i,s_j) and H_bal = ∑_k (∑_i δ(s_i,k) - N/Q)^2, MFC achieves solution quality comparable to strict enforcement while dramatically reducing density; FPGA demonstrations show near two orders-of-magnitude speedups over CPU when communication overhead is minimized. Together, these results map a practical path to scaling constrained optimization on probabilistic hardware, preserving local sparsity and enabling efficient hardware realizations for challenging NP-hard problems.

Abstract

Ising machines and related probabilistic hardware have emerged as promising platforms for NP-hard optimization and sampling. However, many practical problems involve constraints that induce dense or all-to-all couplings, undermining scalability and hardware efficiency. We address this constraint-induced density through two complementary approaches. First, we introduce a hardware-aware native formulation for multi-state probabilistic digits (p-dits) that avoids the locally dense intra-variable couplings required by binary Ising encodings. We validate p-dit dynamics by reproducing known critical behavior of the 2D Potts model. Second, we propose mean-field constraints (MFC), a hybrid scheme that replaces dense pairwise constraint couplings with dynamically updated single-node biases. Applied to balanced graph partitioning, MFC achieves solution quality comparable to exact all-to-all constraint formulations while dramatically reducing graph density. Finally, we demonstrate the practical impact of restored sparsity by an FPGA implementation, enabling orders-of-magnitude acceleration over CPU-based solvers. Together, these results outline a pathway for scaling constrained optimization on probabilistic hardware.

Figures (4)

• Figure 1: Overview of the hybrid probabilistic-classical framework. (a) p-dit state space: A p-dit occupies one of $Q$ discrete states arranged on a ring and proposes transitions only to neighboring states. (b) Update rule: The p-dit computes the local energy of its current state ($E_i$) and a candidate neighbor ($E_i^*$), then transitions probabilistically based on the difference. (c) Hybrid architecture: The probabilistic subsystem handles local interactions. A classical process computes global constraints and broadcasts a bias signal. Both may reside on the same physical fabric, the separation is conceptual. (d) Strict constraints require the classical process to update at every p-dit flip, imposing high synchronization overhead. (e) Mean-field constraints approximate the constraint as a slowly varying field, allowing updates only once per sweep and reducing classical workload while guiding the system toward feasibility.
• Figure 2: Verification of p-dit dynamics using the 2D Potts model. (a) Four-state p-dit showing discrete angular states and allowed transitions between nearest neighbors. (b) 2D Potts lattice used for validation: $L \times L$ square lattice with nearest-neighbor interactions. (c) Finite-size scaling: Measured critical temperatures $T_c(L)$ for $Q=2,3,4$ follow $T_c(L)\approx T_c(\infty)+aL^{-1/\nu}$PhysRevLett.28.1516PhysRevB.30.322PhysRevB.30.1477, consistent with known 2D Potts behavior. (d) Configurations at criticality: Representative $L=100$ configurations for $Q=2,3,4$ at the fitted critical temperatures.
• Figure 3: Mean-field constraints for balanced minimum-cut partitioning. (a) Strictly constrained system: The 4elt mesh encoded with all-to-all constraint couplings. (b) Mean-field formulation: The same problem with dense constraint couplings replaced by a global bias signal (blue arrows). (c) Example result: A 5-way partition of 4elt after $10^{6}$ Monte Carlo sweeps. (d) Dynamics: Evolution of cut size and partition imbalance for strict vs. mean-field constraints, averaged over 100 simulated annealing trials. (e) Benchmarking: Solution quality for 4-way (1% maximum imbalance) and 32-way (2% maximum imbalance) partitions. Dashed lines show reference solutions (Walshaw for 4-way; KaFFPaE for 32-way).
• Figure 4: Hardware performance for balanced min-cut partitioning. Left: Cut-quality convergence for strict constraints, MFC, and FPGA-MFC on a $10\times10\times10$ cube partitioned into three groups (1% maximum imbalance). All approaches converge toward the KaFFPaE reference. Right: Wall-clock runtime vs. Monte Carlo sweeps. FPGA results shown with and without host-device overhead. The FPGA exhibits linear scaling, approaching one p-dit update per clock cycle.