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A Parameterizable Convolution Accelerator for Embedded Deep Learning Applications

Panagiotis Mousouliotis, Georgios Keramidas

TL;DR

The paper tackles the challenge of deploying CNNs for embedded deep learning on resource-limited FPGA SoCs by introducing a parameterizable CNN accelerator template implemented via high-level synthesis. The design comprises a two-part architecture (CONV-PART and MPOOL-PART) with an 8-bit dynamic fixed-point quantization scheme and extensive HW/SW co-design optimizations, enabling latency, power, and area trade-offs across a range of CNN workloads. Key contributions include the detailed accelerator architecture, quantization strategy, HLS-driven parallelism, and an extensive evaluation showing favorable latency and power compared with related works. The work demonstrates a flexible, scalable approach for embedded DL that can be extended to other DL applications and workload families.

Abstract

Convolutional neural network (CNN) accelerators implemented on Field-Programmable Gate Arrays (FPGAs) are typically designed with a primary focus on maximizing performance, often measured in giga-operations per second (GOPS). However, real-life embedded deep learning (DL) applications impose multiple constraints related to latency, power consumption, area, and cost. This work presents a hardware-software (HW/SW) co-design methodology in which a CNN accelerator is described using high-level synthesis (HLS) tools that ease the parameterization of the design, facilitating more effective optimizations across multiple design constraints. Our experimental results demonstrate that the proposed design methodology is able to outperform non-parameterized design approaches, and it can be easily extended to other types of DL applications.

A Parameterizable Convolution Accelerator for Embedded Deep Learning Applications

TL;DR

The paper tackles the challenge of deploying CNNs for embedded deep learning on resource-limited FPGA SoCs by introducing a parameterizable CNN accelerator template implemented via high-level synthesis. The design comprises a two-part architecture (CONV-PART and MPOOL-PART) with an 8-bit dynamic fixed-point quantization scheme and extensive HW/SW co-design optimizations, enabling latency, power, and area trade-offs across a range of CNN workloads. Key contributions include the detailed accelerator architecture, quantization strategy, HLS-driven parallelism, and an extensive evaluation showing favorable latency and power compared with related works. The work demonstrates a flexible, scalable approach for embedded DL that can be extended to other DL applications and workload families.

Abstract

Convolutional neural network (CNN) accelerators implemented on Field-Programmable Gate Arrays (FPGAs) are typically designed with a primary focus on maximizing performance, often measured in giga-operations per second (GOPS). However, real-life embedded deep learning (DL) applications impose multiple constraints related to latency, power consumption, area, and cost. This work presents a hardware-software (HW/SW) co-design methodology in which a CNN accelerator is described using high-level synthesis (HLS) tools that ease the parameterization of the design, facilitating more effective optimizations across multiple design constraints. Our experimental results demonstrate that the proposed design methodology is able to outperform non-parameterized design approaches, and it can be easily extended to other types of DL applications.
Paper Structure (17 sections, 2 equations, 4 figures, 5 tables)

This paper contains 17 sections, 2 equations, 4 figures, 5 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Parameterized Accelerator Template
  4. Supported Operations
  5. Convolution
  6. Optional Activation Layer and Max-Pool
  7. Summary
  8. Architecture
  9. Convolution Part
  10. Max-pool Part
  11. Quantization Strategy
  12. Parallelism Exploitation using HLS
  13. Design Parameters
  14. Application-level Design
  15. Experiments
  16. ...and 2 more sections

Figures (4)

  • Figure 1: Operation of the convolution layer. The number of 3D filters is equal to ${C_o}$, the number of output channels.
  • Figure 2: Accelerator block diagram augmented with HLS optimizations.
  • Figure 3: The accelerator implementation of the MPOOL operation for the case of a $3 \times 3$ filter. The channel dimension is omitted for simplicity.
  • Figure 4: The implementation of the CONV operation.