Characterization of Stitched Prototypes Chip for the ALICE ITS3 Upgrade
Michele Rignanese
TL;DR
The paper assesses stitched 65 nm CMOS MAPS prototypes (babyMOSS) for the ALICE ITS3 upgrade, validated with a CERN PS test-beam campaign using a 10 GeV pion beam. It demonstrates that both non-irradiated and irradiated devices achieve high detection efficiency (>99%), ultra-low fake-hit rates (<10^-6 per pixel per event), and spatial resolutions around 5 μm, meeting ITS3 requirements. The results confirm the viability of wafer-scale stitching, thinning, and cylindrical bending to achieve a low-material, radiation-tolerant vertex detector suitable for ITS3. Together, these findings support the large-scale deployment of stitched MAPS in the ITS3 inner layers, enabling improved tracking performance with a significantly reduced material budget.
Abstract
During LHC Long Shutdown 3, the ALICE experiment will replace the three innermost layers of its Inner Tracking System (ITS2) with a new vertex detector, the ITS3. This new detector will be assembled using wafer-scale, stitched Monolithic Active Pixel Sensors (MAPS) fabricated using a 65nm CMOS technology node, which will be thinned and bent to form truly cylindrical layers around the beam pipe. To validate the new technology, several prototypes were developed and extensively characterized. This work focuses on the results of a test beam campaign performed at the CERN PS in September 2024, using a \SI{10}{\giga\eV} pion beam, to estimate detection efficiency and spatial resolution of the babyMOSS prototype, a smaller version of the MOnolithic Stitched Sensor (MOSS). Both non-irradiated and irradiated chips are tested, and the results confirm that the prototypes meet the ITS3 requirements, demonstrating a detection efficiency above 99\%, with a fake-hit rate below 10$^{-6}$ hits/pixel/event and a spatial resolution around \SI{5}{\micro\meter}.
