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Intrinsically DRC-Compliant Nanophotonic Design via Learned Generative Manifolds

Bahrem Serhat Danis, Demet Baldan Desdemir, Enes Akcakoca, Zeynep Ipek Yanmaz, Gulzade Polat, Ahmet Onur Dasdemir, Aytug Aydogan, Abdullah Magden, Emir Salih Magden

TL;DR

This work tackles the challenge of enforcing fabrication design rules during inverse nanophotonic design by learning a low-dimensional generative manifold of DRC-compliant geometries. By mapping the design search to a latent space $\mathcal{Z}$ through a differentiable generator $G(z)$, optimization becomes $\arg\min_{z} \|F(G(z)) - y^{*}\|^{2}$, ensuring that all candidate designs are fabrication-ready. The generator architecture uses upsampling, softmax with straight-through estimation, and a topological loss to enforce minimum feature sizes and spacings, enabling intrinsic DRC compliance across EBL and PL platforms. Across power splitters, wavelength duplexers, and mode converters in the 1,500–1,600 nm band, the method achieves state-of-the-art performance with significantly faster convergence (e.g., ~5× fewer iterations) and consistent manufacturability. The approach unifies fabrication constraints with topology optimization in a differentiable framework, paving the way for platform-agnostic, foundry-ready nanophotonic design pipelines.

Abstract

Inverse design has enabled the systematic design of ultra-compact and high-performance nanophotonic components. Yet enforcing foundry design rules during inverse design remains a major challenge, as optimized devices frequently violate constraints on minimum feature size and spacing. Existing fabrication-constrained approaches typically rely on penalty terms, projection filters, or heuristic binarization schedules, which restrict the accessible design space, require extensive hyperparameter tuning, and often fail to guarantee compliance throughout the optimization trajectory. Here, we introduce a framework for nanophotonic inverse design with intrinsic enforcement of design rules through a generative reparameterization of the design space, restricting optimization to a learned manifold of DRC-compliant geometries. We validate this paradigm by designing representative silicon photonic components including broadband power splitters, spectral duplexers, and mode converters operating across the 1,500-1,600 nm band for both electron-beam lithography and photolithography platforms. Across all devices, the manifold-based formulation reaches state-of-the-art performance metrics with over a 5-fold reduction in computational cost compared to pixel-based representations, while ensuring fabrication-compatible geometries throughout the entire design process. By treating fabrication constraints as a fundamental property of the design representation rather than an external penalty, this work establishes a direct pathway toward broadly applicable, platform-agnostic, and intrinsically DRC-compliant nanophotonics.

Intrinsically DRC-Compliant Nanophotonic Design via Learned Generative Manifolds

TL;DR

This work tackles the challenge of enforcing fabrication design rules during inverse nanophotonic design by learning a low-dimensional generative manifold of DRC-compliant geometries. By mapping the design search to a latent space through a differentiable generator , optimization becomes , ensuring that all candidate designs are fabrication-ready. The generator architecture uses upsampling, softmax with straight-through estimation, and a topological loss to enforce minimum feature sizes and spacings, enabling intrinsic DRC compliance across EBL and PL platforms. Across power splitters, wavelength duplexers, and mode converters in the 1,500–1,600 nm band, the method achieves state-of-the-art performance with significantly faster convergence (e.g., ~5× fewer iterations) and consistent manufacturability. The approach unifies fabrication constraints with topology optimization in a differentiable framework, paving the way for platform-agnostic, foundry-ready nanophotonic design pipelines.

Abstract

Inverse design has enabled the systematic design of ultra-compact and high-performance nanophotonic components. Yet enforcing foundry design rules during inverse design remains a major challenge, as optimized devices frequently violate constraints on minimum feature size and spacing. Existing fabrication-constrained approaches typically rely on penalty terms, projection filters, or heuristic binarization schedules, which restrict the accessible design space, require extensive hyperparameter tuning, and often fail to guarantee compliance throughout the optimization trajectory. Here, we introduce a framework for nanophotonic inverse design with intrinsic enforcement of design rules through a generative reparameterization of the design space, restricting optimization to a learned manifold of DRC-compliant geometries. We validate this paradigm by designing representative silicon photonic components including broadband power splitters, spectral duplexers, and mode converters operating across the 1,500-1,600 nm band for both electron-beam lithography and photolithography platforms. Across all devices, the manifold-based formulation reaches state-of-the-art performance metrics with over a 5-fold reduction in computational cost compared to pixel-based representations, while ensuring fabrication-compatible geometries throughout the entire design process. By treating fabrication constraints as a fundamental property of the design representation rather than an external penalty, this work establishes a direct pathway toward broadly applicable, platform-agnostic, and intrinsically DRC-compliant nanophotonics.
Paper Structure (7 sections, 3 equations, 7 figures, 1 table)

This paper contains 7 sections, 3 equations, 7 figures, 1 table.

Figures (7)

  • Figure 1: Conceptual illustration of search domains and solution sets in inverse design. The ambient design space is denoted by $\mathcal{X}$. The set $F^{-1}(y^{*})$ corresponds to all permittivity distributions that achieve the desired target response $y^{*}$. The subset $\mathcal{S} \subset \mathcal{X}$ represents the space of fabrication-compatible permittivity distributions. DRC-compliant solutions therefore lie in the intersection of $F^{-1}(y^{*}) \cap \mathcal{S}$. The generative manifold $G(\mathcal{Z})$, parameterized by the latent space $\mathcal{Z}$, is embedded within the subset $\mathcal{S}$, ensuring fabrication compatibility by construction. $G(z)$ denotes one feasible solution within the manifold.
  • Figure 2: DRC-compliant generative model for electron-beam lithography. (a) Schematic of the proposed architecture, illustrating the sequence of operations from a latent variable $z$ to the final device layout. The generator comprises four cascaded upsampling stages followed by three upsampling--convolutional layers, with nonlinear transformations including softmax, thresholding, and morphological closing to ensure design-rule compliance. The straight-through estimator (STE) is employed in the backward pass to preserve gradient flow despite the non-differentiable thresholding step. The generated structure $G(z)$ is evaluated through a design objective (DRC loss) and is iteratively optimized. (b) Training dynamics of the model. The DRC loss decreases from $3 \times 10^{-2}$ to $7 \times 10^{-6}$, representing a reduction by over four orders of magnitude. Insets show representative permittivity distributions at different training stages, with silicon ($n_{\mathrm{Si}}$), silica ($n_{\mathrm{SiO_2}}$), and DRC errors (red circles) highlighted. As training progresses, violations are systematically eliminated, and the final distribution satisfies DRC constraints with no residual errors.
  • Figure 3: Comparison of generator-based and pixel-based inverse design for 50/50 power splitters. (a) Evolution of the loss function and $\Gamma$ during optimization. The generator-based method (red) converges to a loss of $2.8 \times 10^{-4}$ within 149 iterations while maintaining full discreteness of 1 throughout. In contrast, the pixel-based method (black) reaches a lower loss of $1.3 \times 10^{-4}$ after 800 iterations, but requires progressive increases in the projection strength parameter $\beta$ (color-coded, from 8 to 2048) to approach discretization, corresponding to over a 5-fold reduction in computational cost with the generator-based formulation. (b) Transmission spectra of the optimized devices, where solid and dashed lines denote the bottom and top output ports, respectively. (c) Generator-based optimization: snapshots of the permittivity distribution (top) and the corresponding normalized magnetic field $\lvert H_z \rvert$ at $\lambda = 1550$ nm (bottom) across representative iterations. The white contours denote the silicon boundaries. The design remains strictly discrete at every iteration. (d) Pixel-based optimization: analogous snapshots of permittivity (top) and $\lvert H_z \rvert$ fields (bottom), illustrating gradual discretization that is only fully achieved at the final iteration. $\Gamma$ in each snapshot quantitatively tracks this transition.
  • Figure 4: (a) Architectures of generator models designed for two different lithography models. The electron-beam lithography (EBL) model employs a cascaded upsampling architecture with four 1.4$\times$ upsampling stages. This architecture incorporates three upsampling-convolution layers with varying filter sizes (32, 16, and 1) and a $5\times5$ kernel. The output is refined using thresholding and morphological closing layers. (b) The photolithography (PL) model features a similar cascaded upsampling architecture, but with four 1.6$\times$ upsampling stages and two upsampling-convolution layers with a 16.1 filter size and a $7\times7$ kernel. The bottom row of the figure displays the permittivity distributions of a 50/50 power splitter device generated by each model, with footprints of $4.2 \times 4.2~\mu\text{m}^2$ (EBL) and $6 \times 6~\mu\text{m}^2$ (PL). The models are constrained by minimum feature sizes of 60 nm for EBL and 150 nm for PL. The dark blue and white regions represent silicon ($n_{\mathrm{Si}}$) and silicon dioxide ($n_{\mathrm{SiO_2}}$), respectively.
  • Figure 5: Ultrabroadband 70/30 and 90/10 power splitter results designed with the electron-beam lithography generator model. (a) Optimization loss curve for the 30/70 power splitter, showing the loss decreasing to $5 \times 10^{-4}$ over 150 iterations. (b) Transmission curves for the top and bottom ports of the 30/70 power splitter, demonstrating stable performance across the $1500$--$1600$ nm wavelength range. (c) Optimization loss curve for the 10/90 power splitter, converging to a loss of $4 \times 10^{-4}$ after 150 iterations. (d) Transmission curves for the top and bottom ports of the 10/90 power splitter. (e) Permittivity distribution of the 30/70 power splitter (left, with silicon in dark blue and SiO$_2$ in white), alongside the normalized magnetic field ($H_z$) distribution at wavelengths of 1500, 1550, and 1600 nm. The wavelength-insensitive field profiles indicate that the splitting ratio remains constant across the simulated spectrum. (f) Permittivity distribution and normalized magnetic field distribution for the 10/90 power splitter, corresponding to the same wavelengths as in (e).
  • ...and 2 more figures