AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents

TL;DR

AutoSizer tackles the AMS sizing bottleneck by marrying LLM-driven reasoning with a two-loop meta-optimization that adaptively reshapes the search space and orchestrates multiple optimization algorithms. It defines a simulation-driven objective FoM, with $\mathrm{FoM}(\mathbf{y}) = \frac{\prod_{i\in\mathcal{D}} \tilde{y}_i}{\prod_{j\in\mathcal{M}} \tilde{y}_j}$ and $\tilde{y}_i = y_i / y_{i,\text{spec}}$, and enforces feasibility $\tilde{y}_i \ge 1$ for maximizing metrics and $\tilde{y}_j \le 1$ for minimizing ones. The approach uses LLM-based circuit understanding to identify impactful variables, then progressively expands or contracts the search space based on simulation feedback, achieving data-efficient exploration. Experiments on an open SKY130-based AMS-SizingBench (24 circuits) show AutoSizer outperforms traditional methods and prior LLM agents in convergence speed, solution quality, and robustness, with 100% success rate across Easy, Medium, and Hard tasks. The work provides a scalable framework for AI-assisted AMS design and a standardized benchmark for comparing adaptive optimization policies.

Abstract

The design of Analog and Mixed-Signal (AMS) integrated circuits remains heavily reliant on expert knowledge, with transistor sizing a major bottleneck due to nonlinear behavior, high-dimensional design spaces, and strict performance constraints. Existing Electronic Design Automation (EDA) methods typically frame sizing as static black-box optimization, resulting in inefficient and less robust solutions. Although Large Language Models (LLMs) exhibit strong reasoning abilities, they are not suited for precise numerical optimization in AMS sizing. To address this gap, we propose AutoSizer, a reflective LLM-driven meta-optimization framework that unifies circuit understanding, adaptive search-space construction, and optimization orchestration in a closed loop. It employs a two-loop optimization framework, with an inner loop for circuit sizing and an outer loop that analyzes optimization dynamics and constraints to iteratively refine the search space from simulation feedback. We further introduce AMS-SizingBench, an open benchmark comprising 24 diverse AMS circuits in SKY130 CMOS technology, designed to evaluate adaptive optimization policies under realistic simulator-based constraints. AutoSizer experimentally achieves higher solution quality, faster convergence, and higher success rate across varying circuit difficulties, outperforming both traditional optimization methods and existing LLM-based agents.

Figures (5)

• Figure 1: AutoSizer workflow. The framework combines LLM-based circuit understanding with an inner loop that sequentially selects, configures, and applies multiple sizing algorithms and an outer loop that adaptively refines the search space, forming a two-loop closed-loop architecture that enables iterative refinement of variable priorities and parameter ranges based on optimization feedback.
• Figure 2: LLM-generated circuit understanding for the telescopic OTA, including topology analysis, key sizing variables, performance sensitivities, and design trade-offs.
• Figure 3: LLM-generated adaptive search space configuration for the first optimization round, showing variable prioritization, range selection, and dimensionality reduction strategy.
• Figure 4: Search space evaluation and feedback from AutoSizer agent after inner loop finished with 4 optimization iterations.
• Figure 5: AutoSizer's optimization dynamics across three outer loops. (a) Progressive search space changes showing active variables (multiple values) and fixed variables (single value) in each outer loop of the ring oscillator. (b) Convergence trajectory with adaptive algorithm selection (LHS, BO, GA, SA) across inner loop of the ring oscillator. (c) Self-reflection loops and search space reduction ratios across circuit difficulties.