Position: The Need for Ultrafast Training

TL;DR

The paper addresses the mismatch between current inference-focused FPGA accelerators and the need for real-time learning in non-stationary, high-frequency physical systems. It argues for ultrafast on-chip learning that executes gradient updates directly within the FPGA datapath to achieve deterministic latencies below $<1~\mu s$ and fixed-precision operation. It highlights the quantum calibration gap, non-stationary dynamics, and the limitations of host-based RL and interconnect latency, outlining a path toward co-designed algorithms, architectures, and CAD tools. The practical impact includes enabling autonomous quantum calibration, self-tuning scientific instruments, and real-time control in domains ranging from quantum computing to plasma physics, potentially extending qubit coherence and measurement stability. If realized, FPGAs would evolve from static inference engines into real-time learning machines capable of adapting at the speed of underlying physics.

Abstract

Domain-specialized FPGAs have delivered unprecedented performance for low-latency inference across scientific and industrial workloads, yet nearly all existing accelerators assume static models trained offline, relegating learning and adaptation to slower CPUs or GPUs. This separation fundamentally limits systems that must operate in non-stationary, high-frequency environments, where model updates must occur at the timescale of the underlying physics. In this paper, I argue for a shift from inference-only accelerators to ultrafast on-chip learning, in which both inference and training execute directly within the FPGA fabric under deterministic, sub-microsecond latency constraints. Bringing learning into the same real-time datapath as inference would enable closed-loop systems that adapt as fast as the physical processes they control, with applications spanning quantum error correction, cryogenic qubit calibration, plasma and fusion control, accelerator tuning, and autonomous scientific experiments. Enabling such regimes requires rethinking algorithms, architectures, and toolflows jointly, but promises to transform FPGAs from static inference engines into real-time learning machines.