NeuroAI Temporal Neural Networks (NeuTNNs): Microarchitecture and Design Framework for Specialized Neuromorphic Processing Units

TL;DR

This work tackles the challenge of building energy-efficient, brain-inspired AI hardware by bridging neuroscience and AI through NeuroAI. It introduces NeuTNNs, a broader class of Temporal Neural Networks that incorporate active dendrite neurons and reference-frame–based cortical organization, implemented via a six-layer microarchitecture. A key contribution is the NeuTNNGen framework, which automatically translates PyTorch models into CMOS layouts, supports multilayer NeuTNNs, and enables design-space exploration with synaptic pruning to reduce hardware area and leakage while preserving accuracy. The experimental results on UCR time-series benchmarks, MNIST, and Place Cells demonstrate substantial hardware savings (30–50% in pruning scenarios) and competitive accuracy, highlighting NeuTNNs as a viable path for NeuroAI edge accelerators and specialized neuromorphic processing units.

Abstract

Leading experts from both communities have suggested the need to (re)connect research in neuroscience and artificial intelligence (AI) to accelerate the development of next-generation AI innovations. They term this convergence as NeuroAI. Previous research has established temporal neural networks (TNNs) as a promising neuromorphic approach toward biological intelligence and efficiency. We fully embrace NeuroAI and propose a new category of TNNs we call NeuroAI TNNs (NeuTNNs) with greater capability and hardware efficiency by adopting neuroscience findings, including a neuron model with active dendrites and a hierarchy of distal and proximal segments. This work introduces a PyTorch-to-layout tool suite (NeuTNNGen) to design application-specific NeuTNNs. Compared to previous TNN designs, NeuTNNs achieve superior performance and efficiency. We demonstrate NeuTNNGen's capabilities using three example applications: 1) UCR time series benchmarks, 2) MNIST design exploration, and 3) Place Cells design for neocortical reference frames. We also explore using synaptic pruning to further reduce synapse counts and hardware costs by 30-50% while maintaining model precision across diverse sensory modalities. NeuTNNGen can facilitate the design of application-specific energy-efficient NeuTNNs for the next generation of NeuroAI computing systems.

Figures (10)

• Figure 1: Left is the classic point neuron model, and right is the new neuron model with multiple active dendrites. Each active dendrite can contain multiple segments, some distal and some proximal. Each segment is comparable to a point neuron and able to recognize a specific pattern. Figure taken from smith2022macrocolumn.
• Figure 2: NeuroAI Computing Systems embrace the convergence of Neuroscience, AI, and Computer Systems. We fully support and leverage this convergence in our NeuroAI TNN microarchitecture (NeuTNN) and design framework (NeuTNNGen).
• Figure 3: NeuTNNGen framework significantly extends beyond prior TNNGen vellaisamy2024tnngen in functional modeling capabilities and design exploration and synthesis tools. The NeuTNN microarchitecture model consists of a hierarchy of six abstraction layers spanning from synapses up to Cortical (macro) Columns (CC), with support for Active Dendrites (AD).
• Figure 4: NeuTNN microarchitecture organization: Consist of one or more layers, wherein each layer consists of multiple minicolumns stacked in parallel. A minicolumn contains a group of neurons fed by a group of active dendrites. Each blue polygon is a neuron with one or more active dendrites, each containing one or more proximal and/or distal segments. Note that there are two levels of clustering just within a single neuron and three levels of clustering within a single minicolumn.
• Figure 5: NeuTNNGen hardware process flow from RTL generation to layout: Veriloggen converts software model to Verilog, which is simulated using testbench-driven vectors, producing switching activity file. This is sourced during Genus synthesis, along with standard cells and macros. Innovus uses the post-synthesis netlist to generate post-layout netlist and PPA.