Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

System-Level Performance Modeling of Photonic In-Memory Computing

Jebacyril Arockiaraj, Sasindu Wijeratne, Sugeet Sunder, Md Abdullah-Al Kaiser, Akhilesh Jaiswal, Ajey P. Jacob, Viktor Prasanna

TL;DR

The paper presents a comprehensive system-level performance model for photonic in-memory computing using pSRAM, separating latency sources into external memory access and opto-electronic conversion. By defining a network-based abstraction and developing streaming algorithms for Sod shock tube, MTTKRP, and Vlasov–Maxwell workloads, it quantifies how hardware choices affect sustained and peak performance. The results show that a compact 1×256-bit pSRAM array can achieve up to 1.5, 0.9, and 1.3 TOPS with 2.5 TOPS/W energy efficiency, with performance improving under higher memory bandwidth and operating frequency, and scalable benefits from larger arrays. This work provides actionable guidance for co-designing memory, I/O, and photonic compute to approach peak system-level performance in photonic in-memory computing.

Abstract

Photonic in-memory computing is a high-speed, low-energy alternative to traditional transistor-based digital computing that utilizes high photonic operating frequencies and bandwidths. In this work, we develop a comprehensive system-level performance model for photonic in-memory computing, capturing the effects of key latency sources such as external memory access and opto-electronic conversion. We perform algorithm-to-hardware mapping across a range of workloads, including the Sod shock tube problem, Matricized Tensor Times Khatri-Rao Product (MTTKRP), and the Vlasov-Maxwell equation, to evaluate how the latencies impact real-world high-performance computing workloads. Our performance model shows that, while accounting for system overheads, a compact 1x256 bit single-wavelength photonic SRAM array, fabricated using the standard silicon photonics process by GlobalFoundries, sustains up to 1.5 TOPS, 0.9 TOPS, and 1.3 TOPS on the Sod shock tube problem, MTTKRP, and the Vlasov-Maxwell equation with an average energy efficiency of 2.5 TOPS/W.

System-Level Performance Modeling of Photonic In-Memory Computing

TL;DR

The paper presents a comprehensive system-level performance model for photonic in-memory computing using pSRAM, separating latency sources into external memory access and opto-electronic conversion. By defining a network-based abstraction and developing streaming algorithms for Sod shock tube, MTTKRP, and Vlasov–Maxwell workloads, it quantifies how hardware choices affect sustained and peak performance. The results show that a compact 1×256-bit pSRAM array can achieve up to 1.5, 0.9, and 1.3 TOPS with 2.5 TOPS/W energy efficiency, with performance improving under higher memory bandwidth and operating frequency, and scalable benefits from larger arrays. This work provides actionable guidance for co-designing memory, I/O, and photonic compute to approach peak system-level performance in photonic in-memory computing.

Abstract

Photonic in-memory computing is a high-speed, low-energy alternative to traditional transistor-based digital computing that utilizes high photonic operating frequencies and bandwidths. In this work, we develop a comprehensive system-level performance model for photonic in-memory computing, capturing the effects of key latency sources such as external memory access and opto-electronic conversion. We perform algorithm-to-hardware mapping across a range of workloads, including the Sod shock tube problem, Matricized Tensor Times Khatri-Rao Product (MTTKRP), and the Vlasov-Maxwell equation, to evaluate how the latencies impact real-world high-performance computing workloads. Our performance model shows that, while accounting for system overheads, a compact 1x256 bit single-wavelength photonic SRAM array, fabricated using the standard silicon photonics process by GlobalFoundries, sustains up to 1.5 TOPS, 0.9 TOPS, and 1.3 TOPS on the Sod shock tube problem, MTTKRP, and the Vlasov-Maxwell equation with an average energy efficiency of 2.5 TOPS/W.
Paper Structure (31 sections, 13 equations, 7 figures, 1 table, 3 algorithms)

This paper contains 31 sections, 13 equations, 7 figures, 1 table, 3 algorithms.

Table of Contents

  1. Introduction
  2. Photonic SRAM Architecture
  3. Input Encoding
  4. Bitcell
  5. Output Encoding
  6. Target Applications
  7. Sod Shock Tube: Plasma Physics Benchmark
  8. MTTKRP: Canonical Polyadic Tensor Decomposition
  9. Vlasov–Maxwell Equation
  10. System-Level Performance Model
  11. Hardware Modules
  12. System Performance Modeling
  13. Sustained Performance
  14. Peak Performance
  15. Impact of Bit Width on Performance
  16. ...and 16 more sections

Figures (7)

  • Figure 1: Schematic of a 4-bit $(w = 4)$ mixed-signal pSRAM compute cell with inputs scaled based on their bit significance and weight bits stored in the pSRAM bitcells.
  • Figure 2: Overall system illustrating the interaction between external memory (electrical domain), the opto-electronic converter, and the pSRAM array (optical domain).
  • Figure 3: Roofline performance model of the pSRAM array.
  • Figure 4: Impact of peak external memory bandwidth on system performance.
  • Figure 5: Impact of pSRAM operating frequency on system performance.
  • ...and 2 more figures