AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance
Seungkwan Kang, Seungjun Lee, Donghyun Gouk, Miryeong Kwon, Hyunkyu Choi, Junhyeok Jang, Sangwon Lee, Huiwon Choi, Jie Zhang, Wonil Choi, Mahmut Taylan Kandemir, Myoungsoo Jung
TL;DR
AutoGNN tackles the dominant preprocessing bottleneck in GNN inference by moving end-to-end graph preprocessing into FPGA hardware. It introduces Unified Processing Elements (UPEs) for parallel edge ordering and unique sampling and Single-Cycle Reducers (SCRs) for fast counting-based reshaping and reindexing, all supported by dynamic run-time reconfiguration. The design achieves up to 9.0× end-to-end speedup over CPU baselines and 2.1× over GPU-accelerated preprocessing, while reducing power by an order of magnitude during preprocessing and improving memory bandwidth usage. This hardware-software co-design enables robust, low-latency GNN inference across dynamic graphs and diverse datasets, with a cost-model-driven approach to selecting optimal configurations at runtime.
Abstract
Graph neural network (GNN) inference faces significant bottlenecks in preprocessing, which often dominate overall inference latency. We introduce AutoGNN, an FPGA-based accelerator designed to address these challenges by leveraging FPGA's reconfigurability and specialized components. AutoGNN adapts to diverse graph inputs, efficiently performing computationally intensive tasks such as graph conversion and sampling. By utilizing components like adder trees, AutoGNN executes reduction operations in constant time, overcoming the limitations of serialization and synchronization on GPUs. AutoGNN integrates unified processing elements (UPEs) and single-cycle reducers (SCRs) to streamline GNN preprocessing. UPEs enable scalable parallel processing for edge sorting and unique vertex selection, while SCRs efficiently handle sequential tasks such as pointer array construction and subgraph reindexing. A user-level software framework dynamically profiles graph inputs, determines optimal configurations, and reprograms AutoGNN to handle varying workloads. Implemented on a 7$n$m enterprise FPGA, AutoGNN achieves up to 9.0$\times$ and 2.1$\times$ speedup compared to conventional and GPU-accelerated preprocessing systems, respectively, enabling high-performance GNN preprocessing across diverse datasets.
