LocalV: Exploiting Information Locality for IP-level Verilog Generation

TL;DR

This paper tackles the challenge of industrial-scale IP-level RTL generation, where long, detail-rich specifications and the need for correct, synthesizable Verilog code create performance gaps for existing LLM-based approaches. It introduces LocalV, a locality-aware, multi-agent framework that partitions long documents into short tasks, generates concise code fragments, and merges them with a locality-guided debugging loop that traces errors to specific specification fragments via AST analysis. The approach is supported by an information locality hypothesis, quantified by entropy measures, and validated through RealBench and CVDP benchmarks, where LocalV achieves substantial gains (e.g., 45.0% pass rate on RealBench vs 21.6% SOTA; 61.50% on CVDP) and competitive PPA metrics. The results demonstrate that focusing on localized information and fragment-based generation reduces contextual overhead and improves reliability and efficiency in IP-level RTL design, offering a practical pathway for industrial HDL automation with LLMs.

Abstract

The generation of Register-Transfer Level (RTL) code is a crucial yet labor-intensive step in digital hardware design, traditionally requiring engineers to manually translate complex specifications into thousands of lines of synthesizable Hardware Description Language (HDL) code. While Large Language Models (LLMs) have shown promise in automating this process, existing approaches-including fine-tuned domain-specific models and advanced agent-based systems-struggle to scale to industrial IP-level design tasks. We identify three key challenges: (1) handling long, highly detailed documents, where critical interface constraints become buried in unrelated submodule descriptions; (2) generating long RTL code, where both syntactic and semantic correctness degrade sharply with increasing output length; and (3) navigating the complex debugging cycles required for functional verification through simulation and waveform analysis. To overcome these challenges, we propose LocalV, a multi-agent framework that leverages information locality in modular hardware design. LocalV decomposes the long-document to long-code generation problem into a set of short-document, short-code tasks, enabling scalable generation and debugging. Specifically, LocalV integrates hierarchical document partitioning, task planning, localized code generation, interface-consistent merging, and AST-guided locality-aware debugging. Experiments on RealBench, an IP-level Verilog generation benchmark, demonstrate that LocalV substantially outperforms state-of-the-art (SOTA) LLMs and agents, achieving a pass rate of 45.0% compared to 21.6%.

Figures (11)

• Figure 1: Performance of Claude 3.7 Sonnet on RealBench: Pass@k vs. (a) I/O signal count and (b) code length (lines), reporting syntactic and functional Pass@k. Accuracy decreases with interface complexity and output length.
• Figure 2: Workflow overview of LocalV.
• Figure 3: Heatmaps of normalized similarity across three tasks. Columns represent code units, with values independently scaled [0, 1] to show cosine similarity to all document paragraphs; lower values indicate higher information locality. (a) 10 randomly selected and combined modules from VerilogEval: Extremely high locality ($\bar{H}_{\mathrm{norm}} = 0.6366$) due to module independence. (b) E203 CPU Top Module from RealBench: High information locality ($\bar{H}_{\mathrm{norm}} = 0.6718$). (c) Parse Lisp Expression problem: Typical software task with lower locality ($\bar{H}_{\mathrm{norm}} = 0.8220$). (d) Illustration of cosine similarity between a single E203 CPU code unit and all document paragraphs.
• Figure 4: The detailed workflow of LocalV. (a) Output of the planning stage, illustrating the structure of a sub-task. (b) Overview of the code generation and merging process. (c) Overview of the debugging loop and the generation of the final code.
• Figure 5: Distribution of syntactic error types for Claude 3.7 Sonnet and LocalV.