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Weight-four parity checks with silicon spin qubits

Brennan Undseth, Nicola Meggiato, Yi-Hsien Wu, Sam R. Katiraee-Far, Larysa Tryputen, Sander L. de Snoo, Davide Degli Esposti, Giordano Scappucci, Eliška Greplová, Lieven M. K. Vandersypen

Abstract

Recent advances in coherent spin shuttling have made sparse semiconductor spin qubit arrays an appealing solid-state platform to realize quantum processors. The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction (QEC) schemes. Here, we demonstrate a silicon spin-qubit device that comprises a shuttling bus for coherently transporting qubits that can interact at four isolated locations we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition (QND) spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X- and Z-type parity checks up to weight-four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger-Horne-Zeilinger (GHZ) state, constituting the largest such state ever constructed with gate-defined semiconductor spins. This work opens immediate opportunities to pursue QEC experiments with spin qubits, and the protocols developed here lay the groundwork for the modular calibration and operation of sparse spin qubit arrays.

Weight-four parity checks with silicon spin qubits

Abstract

Recent advances in coherent spin shuttling have made sparse semiconductor spin qubit arrays an appealing solid-state platform to realize quantum processors. The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction (QEC) schemes. Here, we demonstrate a silicon spin-qubit device that comprises a shuttling bus for coherently transporting qubits that can interact at four isolated locations we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition (QND) spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X- and Z-type parity checks up to weight-four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger-Horne-Zeilinger (GHZ) state, constituting the largest such state ever constructed with gate-defined semiconductor spins. This work opens immediate opportunities to pursue QEC experiments with spin qubits, and the protocols developed here lay the groundwork for the modular calibration and operation of sparse spin qubit arrays.
Paper Structure (19 sections, 9 equations, 22 figures, 2 tables)

This paper contains 19 sections, 9 equations, 22 figures, 2 tables.

Figures (22)

  • Figure 1: Device concept and shuttling bus. a False-colored scanning electron microscope image of a device nominally identical to that used in the experiments. Four metallization layers (from bottom to top: blue, red, yellow, green) are used to define a single-electron transistor charge sensor (S1), the readout zone (B0-P2), the shuttling bus (C0-C14), and four bus stops (BP1-BP4). The readout zone on the right side of the device (P3-B3) is functional but unused, and no electrons are accumulated beneath P3 or P4. A partially-magnetized cobalt micromagnet (gray) provides an inhomogeneous magnetic field profile to define and operate the qubits. No external magnetic field is present. The colored spins correspond to the qubit labels in b. b The qubit connectivity graph made possible via the shuttling bus. Solid lines indicate connections used in this work, whereby the shuttled ancilla qubit (A1) may interact with the four data qubits (D1-D4) as well as the readout ancilla (R1). This connectivity forms a surface code stabilizer plaquette in the context of a larger architecture. Dashed lines indicate connections that are physically available but unused in this work. c The simulated and measured Larmor frequency profile along the shuttling bus axis. Analogous values for a spin localized under the bus stop plungers (BP1-BP4) are plotted at the adjacent shuttling bus gates (C1-C13) and highlighted by the respective colors depicted in a.
  • Figure 2: Remote tuning protocols. a Illustration of the remote tuning concept. The sensor has a limited charge sensing range and is therefore only used for qubit measurement of the ancilla spin. To probe control of the bus stops, the ancilla is shuttled beyond charge sensing range, and spin physics is used to calibrate the virtual detuning $v\epsilon \propto \mu_1-\mu_2$ and average chemical potential $vU\propto \left(\mu_1+\mu_2\right)/2$ for all four effective double-dot systems formed at the bus stops (see Sec. \ref{['supp:1etuning']}). b An example of a Ramsey tunneling experiment at bus stop 3. Coherent tunneling of the ancilla spin from the shuttling bus to the bus stop is recognized by the abrupt change in Larmor precession frequency. Colorbars are shared with c-f. c-f Examples of charge transitions identified via Ramsey tunneling experiments for bus stops 1-4 respectively with wait times on the order of tens of nanoseconds. The interdot charge transition between the shuttling bus and bus stop 3 which may be used to infer control of $v\epsilon$ and $vU$ is shown in e, while the other scans are used to extract other virtual gate matrix elements. g Crosstalk heatmap with respect to the interdot charge transition between the bus and each bus stop extracted from scans analogous to those in c-f (see Fig. \ref{['fig:sparse_crosstalk']}). Detectable crosstalk to multiple bus stops is indicated by split coloring. h An effective two-electron charge stability diagram of the isolated double dot system formed at bus stop 2 identified from the returned polarization of a shuttled spin. i Detection of the exchange interaction strength $J_2$ between a shuttled spin and a mixed spin state in bus stop 2 obtained by applying microwave bursts at the charge symmetry point as determined from h. See Fig. \ref{['fig:bus_stop_calibrations']} for analogous calibrations of all four bus stops.
  • Figure 3: QND measurement framework and QPU characterization. a Schematic showing the overall protocol for loading, initializing, measuring, and unloading the sparse array when used as a quantum processor. b Building block of the loading protocol. The ancilla qubit is shuttled along the bus, tunnels into the selected bus stop, and is relabeled as a data qubit. A new ancilla is then reloaded from S1 as described in Sec. \ref{['supp:reload']}. c Building block of the initialization protocol. Two rounds of QND measurements are performed on the data qubit, with real-time feedback used to correct the measured state of both the ancilla and data qubits. Post-selection is used to further boost the initialization fidelity by filtering certain error modes, such as infidelity in the CROT. A variable number of data qubits can be initialized in any order using this fixed building block at the expense of some redundancy, but this does not cause a meaningful performance bottleneck. d Building block of the QND readout protocol. Extraction of the five-qubit computational-basis measurement is elaborated in Sec. \ref{['supp:QNDmeasurement']}. e CPMG coherence time measured for the ancilla qubit and four data qubits. Fits are according to an assumed $1/f^\alpha$ noise power spectral density (see Sec. \ref{['supp:1Qcharacterization']}). f Exchange tunability of all four interactions between data qubits and the ancilla. Fits assume an exponential relation between barrier voltage and exchange. g Overview of all benchmarked operations and qubit properties in the five-qubit processor (see Sec. \ref{['supp:1Qcharacterization']} and \ref{['supp:2Qcharacterization']}).
  • Figure 4: Benchmarking parity checks and multi-qubit entanglement. a Quantum circuit depicting the multi-qubit decoupled CZ used for coherent two-qubit operations. The circuit generalizes to any number $w$ of data qubits by omitting or adding quantum wires of different data qubits. Single-qubit gates are parallelized pairwise when relevant, and the $2w$$S$ gates are applied virtually. b Quantum circuit depicting a weight-four $Z$-type parity check utilizing the multi-qubit decoupled CZ from a. The circuit generalizes to any number of data qubits by changing the weight $w$ of the decoupled CZ. An $X$-type check is performed with the inclusion of the dashed Hadamard gates. c Quantum circuit depicting $w$-qubit GHZ state generation using an $X$-type parity check. The dashed line indicates when the ancilla forms a $w+1$-qubit GHZ state with the data qubits. The outcome of the ancilla measurement determines which of two GHZ states are realized in the data qubits. One of the two outcomes can be used as a logical state of a four-qubit quantum error correction code. d Outcomes of the weight-four $Z$-type ($X$-type) parity check obtained after preparing all $Z$-basis ($X$-basis) eigenstates of the data qubits. The black wireframes indicate the ideal result for each input state, and we estimate that data qubit initialization errors contribute a discrepancy of 2% in the observed ancilla outcome. All other parity checks are shown in Fig. \ref{['fig:paritychecks']}. e The parity check accuracy for all $Z$- and $X$-type parity checks of weights two through four computed as the average probability that the ancilla measurement is correct and the data qubits are measured in the intended prepared state. Data qubit initialization and readout errors are removed by rescaling, and error bars signify $\pm1\sigma$ as determined by Monte Carlo bootstrapping (see Sec. \ref{['supp:paritychecks']}). f GHZ state fidelities for all combinations of two or more qubits in the five qubit processor (some overlap closely). State fidelities including the ancilla are calculated with respect to the GHZ state $\frac{1}{\sqrt{2}}(\ket{0}^{\otimes (w+1)}+\ket{1}^{\otimes (w+1)})$. For GHZ states initialized via a weight-$w$ parity check, the state fidelities are calculated with respect to $\frac{1}{\sqrt{2}}(\ket{0}^{\otimes w}\pm\ket{1}^{\otimes w})$. Error bars signify $\pm 1\sigma$ as determined by Monte Carlo bootstrapping (see Sec. \ref{['supp:QST']}). All reconstructed density matrices are shown in Fig. \ref{['fig:rhos_Q2']}, Fig. \ref{['fig:rhos_Q3']}, Fig. \ref{['fig:rhos_Q4']} and Fig. \ref{['fig:rhos_Q5']} along with the estimated fidelities in the absence of initialization and readout error removal.
  • Figure 5: a-d First signatures of remote single-electron charge transitions measured within the four bus stops when exploring the empty array by shuttling a spin in superposition before gate virtualization or tunnel coupling tuning had taken place. e-h Remote single-electron charge transitions measured within the four bus stops after virtualizing control of each effective double-dot system and increasing the tunnel coupling. A fixed ramp time of 40ns was used, therefore the tunneled spin picks up a phase that depends on the magnitude of the detuning pulse. The Larmor precession frequency in each dot is effectively constant. i-l Remote two-electron charge stability diagrams measured for all four bus stops when all other bus stops are populated with a single-electron. Multiple features parallel to the charge transition line likely indicate tunneling to excited orbital states. m-p Exchange splitting measured with EDSR for all four bus stops when all other bus stops are populated with a single electron. The four bus stops are color-coded for clarity, but the measured signal is the probability of an odd-parity PSB outcome $P_\mathrm{odd}$ in all cases.
  • ...and 17 more figures