Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms

TL;DR

This work tackles the vulnerability of the Number Theoretic Transform (NTT) in lattice-based PQC to hardware Trojans and SASCA by introducing a secure NTT architecture. It combines control-flow integrity via a backup control status register and an independent right-shift register, a clock-cycle counter to detect unconventional delays, and a local masking scheme to mitigate SASCA, complemented by an adaptive fault-correction module that uses multiple preloaded bitstreams and a host-driven bit patcher to select the lowest-risk configuration. The approach demonstrates robust fault detection and correction on Artix-7 FPGAs with Kyber variants, incurring modest area and energy overheads while maintaining timing, and shows resilience against various Trojan placement scenarios. Practically, this enables more secure and reliable PQC deployments on reconfigurable platforms where control signals are a common Trojan target and timing integrity is critical. The work also outlines a path toward broader integration of adaptive fault tolerance across PQC primitives in future security processors.

Abstract

Number Theoretic Transform (NTT) is the most essential component for polynomial multiplications used in lattice-based Post-Quantum Cryptography (PQC) algorithms such as Kyber, Dilithium, NTRU etc. However, side-channel attacks (SCA) and hardware vulnerabilities in the form of hardware Trojans may alter control signals to disrupt the circuit's control flow and introduce unconventional delays in the critical hardware of PQC. Hardware Trojans, especially on control signals, are more low cost and impactful than data signals because a single corrupted control signal can disrupt or bypass entire computation sequences, whereas data faults usually cause only localized errors. On the other hand, adversaries can perform Soft Analytical Side Channel Attacks (SASCA) on the design using the inserted hardware Trojan. In this paper, we present a secure NTT architecture capable of detecting unconventional delays, control-flow disruptions, and SASCA, while providing an adaptive fault-correction methodology for their mitigation. Extensive simulations and implementations of our Secure NTT on Artix-7 FPGA with different Kyber variants show that our fault detection and correction modules can efficiently detect and correct faults whether caused unintentionally or intentionally by hardware Trojans with a high success rate, while introducing only modest area and time overheads.

Figures (9)

• Figure 1: Control and Status Signals of NTT
• Figure 2: Right Shift Register
• Figure 3: Timing Diagram of Our Secure NTT
• Figure 4: Pipeline Stages of proposed Secure NTT
• Figure 5: Architecture of Secure NTT with Fault Detection Module