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AscendCraft: Automatic Ascend NPU Kernel Generation via DSL-Guided Transcompilation

Zhongzhen Wen, Shudi Shao, Zhong Li, Yu Ge, Tongtong Xu, Yuanyi Lin, Tian Zhang

TL;DR

AscendCraft introduces a DSL-guided, two-stage approach to automatic AscendC kernel generation for NPUs, addressing the difficulties of direct LLM-based generation under AscendC constraints. A lightweight DSL captures host planning, on-chip execution, and dataflow with explicit tiling and memory semantics, while a multi-pass transcompilation pipeline translates DSL programs into valid AscendC kernels with tight structural constraints. Evaluations on MultiKernelBench show high compilation (98.1%) and correctness (90.4%), with many kernels achieving substantial performance relative to PyTorch eager execution (up to $$0.2$$–$${0.8},{1.0}$ Fast targets). A real-world mHC kernel case demonstrates strong generalization and significant speedups, illustrating that DSL-guided transcompilation can provide practical, scalable support for Nuanced NPU workloads and future kernel development workflows.

Abstract

The performance of deep learning models critically depends on efficient kernel implementations, yet developing high-performance kernels for specialized accelerators remains time-consuming and expertise-intensive. While recent work demonstrates that large language models (LLMs) can generate correct and performant GPU kernels, kernel generation for neural processing units (NPUs) remains largely underexplored due to domain-specific programming models, limited public examples, and sparse documentation. Consequently, directly generating AscendC kernels with LLMs yields extremely low correctness, highlighting a substantial gap between GPU and NPU kernel generation. We present AscendCraft, a DSL-guided approach for automatic AscendC kernel generation. AscendCraft introduces a lightweight DSL that abstracts non-essential complexity while explicitly modeling Ascend-specific execution semantics. Kernels are first generated in the DSL using category-specific expert examples and then transcompiled into AscendC through structured, constraint-driven LLM lowering passes. Evaluated on MultiKernelBench across seven operator categories, AscendCraft achieves 98.1% compilation success and 90.4% functional correctness. Moreover, 46.2% of generated kernels match or exceed PyTorch eager execution performance, demonstrating that DSL-guided transcompilation can enable LLMs to generate both correct and competitive NPU kernels. Beyond benchmarks, AscendCraft further demonstrates its generality by successfully generating two correct kernels for newly proposed mHC architecture, achieving performance that substantially surpasses PyTorch eager execution.

AscendCraft: Automatic Ascend NPU Kernel Generation via DSL-Guided Transcompilation

TL;DR

AscendCraft introduces a DSL-guided, two-stage approach to automatic AscendC kernel generation for NPUs, addressing the difficulties of direct LLM-based generation under AscendC constraints. A lightweight DSL captures host planning, on-chip execution, and dataflow with explicit tiling and memory semantics, while a multi-pass transcompilation pipeline translates DSL programs into valid AscendC kernels with tight structural constraints. Evaluations on MultiKernelBench show high compilation (98.1%) and correctness (90.4%), with many kernels achieving substantial performance relative to PyTorch eager execution (up to –$ Fast targets). A real-world mHC kernel case demonstrates strong generalization and significant speedups, illustrating that DSL-guided transcompilation can provide practical, scalable support for Nuanced NPU workloads and future kernel development workflows.

Abstract

The performance of deep learning models critically depends on efficient kernel implementations, yet developing high-performance kernels for specialized accelerators remains time-consuming and expertise-intensive. While recent work demonstrates that large language models (LLMs) can generate correct and performant GPU kernels, kernel generation for neural processing units (NPUs) remains largely underexplored due to domain-specific programming models, limited public examples, and sparse documentation. Consequently, directly generating AscendC kernels with LLMs yields extremely low correctness, highlighting a substantial gap between GPU and NPU kernel generation. We present AscendCraft, a DSL-guided approach for automatic AscendC kernel generation. AscendCraft introduces a lightweight DSL that abstracts non-essential complexity while explicitly modeling Ascend-specific execution semantics. Kernels are first generated in the DSL using category-specific expert examples and then transcompiled into AscendC through structured, constraint-driven LLM lowering passes. Evaluated on MultiKernelBench across seven operator categories, AscendCraft achieves 98.1% compilation success and 90.4% functional correctness. Moreover, 46.2% of generated kernels match or exceed PyTorch eager execution performance, demonstrating that DSL-guided transcompilation can enable LLMs to generate both correct and competitive NPU kernels. Beyond benchmarks, AscendCraft further demonstrates its generality by successfully generating two correct kernels for newly proposed mHC architecture, achieving performance that substantially surpasses PyTorch eager execution.
Paper Structure (45 sections, 3 figures, 2 tables)

This paper contains 45 sections, 3 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Ascend NPU Architecture
  4. Compute Units.
  5. Memory Hierarchy.
  6. Data Movement and Transfer Mechanism.
  7. Instruction Pipelining.
  8. AscendC Programming Model
  9. Execution and Pipeline Model.
  10. Tensor and Buffer Management.
  11. Queues and Data Dependency Management.
  12. Operations and Programming Complexity.
  13. LLM for Kernel Generation
  14. LLMs for GPU Kernel Generation.
  15. Challenges in NPU Kernel Generation.
  16. ...and 30 more sections

Figures (3)

  • Figure 1: Ascend architecture.
  • Figure 2: An example of a Softmax kernel written in the proposed Ascend DSL. The example shows the separation between host-side execution planning and kernel-side on-chip computation, as well as the staged execution pattern (copyin, compute, copyout). It demonstrates how the DSL expresses tiled computation, on-chip buffer usage, and core dataflow logic while abstracting low-level AscendC details.
  • Figure 3: Framework of AscendCraft.