RulePlanner: All-in-One Reinforcement Learner for Unifying Design Rules in 3D Floorplanning

TL;DR

RulePlanner tackles the challenging problem of 3D IC floorplanning under multiple real-world hardware design rules by unifying rule handling into an all-in-one reinforcement learning framework. It introduces novel matrix representations (e.g., adjacent terminal and adjacent block masks), direct action-space constraints through an availability mask, and a dense, self-adaptively normalized reward that jointly accounts for rule satisfaction, HPWL, and overlap. The architecture combines a Transformer-based netlist processor with a vision-based module to process rule matrices, and trains under a hybrid action space with PPO, achieving strong zero-shot generalization and transferability to unseen circuits while enabling easy extensibility for new rules. Empirical results on public benchmarks demonstrate RulePlanner’s ability to satisfy complex constraints concurrently and to outperform baselines on design-rule metrics, illustrating potential for practical IC design automation and scalability to future challenges, with code to be released at the project repository.

Abstract

Floorplanning determines the coordinate and shape of each module in Integrated Circuits. With the scaling of technology nodes, in floorplanning stage especially 3D scenarios with multiple stacked layers, it has become increasingly challenging to adhere to complex hardware design rules. Current methods are only capable of handling specific and limited design rules, while violations of other rules require manual and meticulous adjustment. This leads to labor-intensive and time-consuming post-processing for expert engineers. In this paper, we propose an all-in-one deep reinforcement learning-based approach to tackle these challenges, and design novel representations for real-world IC design rules that have not been addressed by previous approaches. Specifically, the processing of various hardware design rules is unified into a single framework with three key components: 1) novel matrix representations to model the design rules, 2) constraints on the action space to filter out invalid actions that cause rule violations, and 3) quantitative analysis of constraint satisfaction as reward signals. Experiments on public benchmarks demonstrate the effectiveness and validity of our approach. Furthermore, transferability is well demonstrated on unseen circuits. Our framework is extensible to accommodate new design rules, thus providing flexibility to address emerging challenges in future chip design. Code will be available at: https://github.com/Thinklab-SJTU/EDA-AI

Figures (12)

• Figure 1: Demonstration of hardware design rules. Specialized rules (a-d) are emphasized, while other general rules (e-g) should be satisfied by all blocks.
• Figure 2: Pipeline of our approach. Stacked design rule matrices and netlist graph are taken as the input features. Hybrid action $(x,y,\mathrm{AR})$ is determined by policy network, and is further processed to filter out invalid positions and aspect ratio range, ensuring compliance with design rules.
• Figure 3: Left: the adjacent terminal mask, where each element with location $(x,y)$ indicates the distance $d(b,t)$ between terminal $t$ and block $b$ if we place $b$ at $(x,y)$. Right: the binary adjacent terminal mask, where the yellow region indicates valid positions to place block $b$ adhering to the boundary constraint. For instance, we place block $b$ at the blue point, where terminal $t$ is adjacent to it. Note that for better visualization, we move the terminal into the floorplan region instead of along the boundary.
• Figure 4: Left: The adjacent block mask for block $b_i$ (green), where each element $(x, y)$ represents the adjacency length $l(b_i, b_j)$ between $b_i$ and its placed adjacent block $b_j$ (blue). Right: The binary adjacent block mask, with the yellow region denoting valid positions for placing $b_i$ such that it is physically abutted to its adjacent block $b_j$, thereby satisfying the grouping constraint.
• Figure 5: Demonstration of chip floorplan layout and all masks for the availability mask. In sub-figures 'Floorplan, Layer=0/1', current block to place is highlighted with blue, while gray blocks have already been placed. Red points represent the normal terminals, and the blue points indicate the terminals with which specific blocks should align. Adj: adjacent. Bin: binary.

Theorems & Definitions (7)

• Definition 3.1
• Definition 3.2
• Definition 3.3
• Definition 3.4
• Definition 2.1
• Definition 2.2
• Definition 2.3