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Late Breaking Results: Conversion of Neural Networks into Logic Flows for Edge Computing

Daniel Stein, Shaoyi Huang, Rolf Drechsler, Bing Li, Grace Li Zhang

TL;DR

The paper addresses the challenge of running large, MAC-heavy neural networks on resource-constrained edge CPUs. It introduces a method to convert networks into logic flows by building an equivalent decision-tree representation from training data, extracting constant-leaf paths via mixed-integer programming and irreducible infeasible subsystem analysis, and then executing these paths as logic flows in a hybrid CPU workflow. Experimental results on three quantized networks across MNIST and occupancy datasets show no accuracy degradation and substantial latency reductions on a RISC-V simulator, with minimum latency improvements up to 52.2% and selective-layer improvements up to 39.3%. An open-source implementation enables practical deployment and demonstrates a new approach for accelerating neural computations on edge devices using CPU-based logic flow execution.

Abstract

Neural networks have been successfully applied in various resource-constrained edge devices, where usually central processing units (CPUs) instead of graphics processing units exist due to limited power availability. State-of-the-art research still focuses on efficiently executing enormous numbers of multiply-accumulate (MAC) operations. However, CPUs themselves are not good at executing such mathematical operations on a large scale, since they are more suited to execute control flow logic, i.e., computer algorithms. To enhance the computation efficiency of neural networks on CPUs, in this paper, we propose to convert them into logic flows for execution. Specifically, neural networks are first converted into equivalent decision trees, from which decision paths with constant leaves are then selected and compressed into logic flows. Such logic flows consist of if and else structures and a reduced number of MAC operations. Experimental results demonstrate that the latency can be reduced by up to 14.9 % on a simulated RISC-V CPU without any accuracy degradation. The code is open source at https://github.com/TUDa-HWAI/NN2Logic

Late Breaking Results: Conversion of Neural Networks into Logic Flows for Edge Computing

TL;DR

The paper addresses the challenge of running large, MAC-heavy neural networks on resource-constrained edge CPUs. It introduces a method to convert networks into logic flows by building an equivalent decision-tree representation from training data, extracting constant-leaf paths via mixed-integer programming and irreducible infeasible subsystem analysis, and then executing these paths as logic flows in a hybrid CPU workflow. Experimental results on three quantized networks across MNIST and occupancy datasets show no accuracy degradation and substantial latency reductions on a RISC-V simulator, with minimum latency improvements up to 52.2% and selective-layer improvements up to 39.3%. An open-source implementation enables practical deployment and demonstrates a new approach for accelerating neural computations on edge devices using CPU-based logic flow execution.

Abstract

Neural networks have been successfully applied in various resource-constrained edge devices, where usually central processing units (CPUs) instead of graphics processing units exist due to limited power availability. State-of-the-art research still focuses on efficiently executing enormous numbers of multiply-accumulate (MAC) operations. However, CPUs themselves are not good at executing such mathematical operations on a large scale, since they are more suited to execute control flow logic, i.e., computer algorithms. To enhance the computation efficiency of neural networks on CPUs, in this paper, we propose to convert them into logic flows for execution. Specifically, neural networks are first converted into equivalent decision trees, from which decision paths with constant leaves are then selected and compressed into logic flows. Such logic flows consist of if and else structures and a reduced number of MAC operations. Experimental results demonstrate that the latency can be reduced by up to 14.9 % on a simulated RISC-V CPU without any accuracy degradation. The code is open source at https://github.com/TUDa-HWAI/NN2Logic
Paper Structure (7 sections, 1 figure, 1 table)

This paper contains 7 sections, 1 figure, 1 table.

Table of Contents

  1. Introduction
  2. Methodology
  3. Conversion into Decision Trees with Training Data
  4. Selection of Decision Paths for Extracting Logic Flows
  5. Hybrid Execution with Selected Decision Paths
  6. Experimental Results
  7. Conclusion

Figures (1)

  • Figure 1: Conversion of a neural network into an equivalent decision tree. (a) A neural network for binary classification (classes $c_0$ and $c_1$). (b) The decision tree of the neural network in (a) constructed using training data. (c) C Code for hybrid execution of the neural network and the logic flow of leaf L4.