Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence

Saoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Soroosh Noorzad, Morteza Fayazi

TL;DR

The paper tackles the challenge of converting circuit schematic images into machine-readable netlists, addressing limitations in component recognition, connectivity inference, and text extraction. It introduces SINA, an open-source pipeline that fuses a YOLOv11-based component detector, Connected-Component Labeling for wiring connectivity, EasyOCR for text extraction, and a GPT-4o Vision-Language Model for reliable designator assignment to produce SPICE-compatible netlists. The approach achieves 96.47% netlist-generation accuracy and outperforms state-of-the-art methods by approximately 2.72x on a curated benchmark, enabling scalable dataset creation for AI-driven EDA workflows across diverse schematic styles. This work facilitates automated, robust extraction of circuit information from visuals, with practical impact for researchers and practitioners seeking to reuse schematics from literature and media.

Abstract

Current methods for converting circuit schematic images into machine-readable netlists struggle with component recognition and connectivity inference. In this paper, we present SINA, an open-source, fully automated circuit schematic image-to-netlist generator. SINA integrates deep learning for accurate component detection, Connected-Component Labeling (CCL) for precise connectivity extraction, and Optical Character Recognition (OCR) for component reference designator retrieval, while employing a Vision-Language Model (VLM) for reliable reference designator assignments. In our experiments, SINA achieves 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.

SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence

TL;DR

The paper tackles the challenge of converting circuit schematic images into machine-readable netlists, addressing limitations in component recognition, connectivity inference, and text extraction. It introduces SINA, an open-source pipeline that fuses a YOLOv11-based component detector, Connected-Component Labeling for wiring connectivity, EasyOCR for text extraction, and a GPT-4o Vision-Language Model for reliable designator assignment to produce SPICE-compatible netlists. The approach achieves 96.47% netlist-generation accuracy and outperforms state-of-the-art methods by approximately 2.72x on a curated benchmark, enabling scalable dataset creation for AI-driven EDA workflows across diverse schematic styles. This work facilitates automated, robust extraction of circuit information from visuals, with practical impact for researchers and practitioners seeking to reuse schematics from literature and media.

Abstract

Current methods for converting circuit schematic images into machine-readable netlists struggle with component recognition and connectivity inference. In this paper, we present SINA, an open-source, fully automated circuit schematic image-to-netlist generator. SINA integrates deep learning for accurate component detection, Connected-Component Labeling (CCL) for precise connectivity extraction, and Optical Character Recognition (OCR) for component reference designator retrieval, while employing a Vision-Language Model (VLM) for reliable reference designator assignments. In our experiments, SINA achieves 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.
Paper Structure (8 sections, 2 figures, 2 tables)

This paper contains 8 sections, 2 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Proposed Framework
  3. Component Detection
  4. Connectivity Inference
  5. Reference Designator Extraction and Assignment
  6. Netlist Generation
  7. Evaluation
  8. Conclusion

Figures (2)

  • Figure 1: The proposed SINA's workflow.
  • Figure 2: An example of SINA's pipeline. (a) The original circuit schematic image. (b) The detection model output with identified components and their bounding boxes. (c) Removing components and clustering nodes. (d) Nodes and their connections to the components. (e) The final generated netlist.