PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converters

TL;DR

PowerGenie tackles the exponential design-space challenge of reconfigurable power converters by pairing an automated analytical framework with an evolutionary finetuning loop that co-evolves a generative model and its training distribution. It uses graph-based analysis and Tellegen's theorem to compute $M_{SSL}$, $M_{FSL}$, and a figure-of-merit (FoM) without SPICE sizing, enabling rapid, large-scale evaluation. The method discovers genuinely superior topologies—most notably an 8-mode converter with FoM exceeding the training set by 23% and SPICE-validated efficiency gains up to 17% in certain modes. This approach demonstrates scalable, performance-driven design automation for complex analog/mixed-signal topologies and sets the stage for extension to other switched-capacitor circuits.

Abstract

Discovering superior circuit topologies requires navigating an exponentially large design space-a challenge traditionally reserved for human experts. Existing AI methods either select from predefined templates or generate novel topologies at a limited scale without rigorous verification, leaving large-scale performance-driven discovery underexplored. We present PowerGenie, a framework for automated discovery of higher-performance reconfigurable power converters at scale. PowerGenie introduces: (1) an automated analytical framework that determines converter functionality and theoretical performance limits without component sizing or SPICE simulation, and (2) an evolutionary finetuning method that co-evolves a generative model with its training distribution through fitness selection and uniqueness verification. Unlike existing methods that suffer from mode collapse and overfitting, our approach achieves higher syntax validity, function validity, novelty rate, and figure-of-merit (FoM). PowerGenie discovers a novel 8-mode reconfigurable converter with 23% higher FoM than the best training topology. SPICE simulations confirm average absolute efficiency gains of 10% across 8 modes and up to 17% at a single mode. Code is available at https://github.com/xz-group/PowerGenie.

Figures (8)

• Figure 1: (a) Power converters bridge energy sources to applications spanning AI infrastructure, EVs, and mobile devices. (b) PowerGenie discovers topologies beyond the training Pareto front.
• Figure 2: (a) A 3-mode reconfigurable SC converter designed by human experts le201032nm, merging three independent single-mode topologies into a unified structure. (b) Corresponding 6-bit control configurations for each MOSFET across VCR modes and phases, where 1 indicates on and 0 indicates off.
• Figure 3: Analytical framework demonstration using a single-mode two-phase converter (VCR=1/3). (a) Topology. (b) Phase networks with spanning trees, fundamental loops, and cutsets. (c) VCR and capacitor voltage extraction via KVL. (d) Charge multiplier extraction via KCL. Switch charge multipliers and blocking voltages follow similarly by including switches in the phase graphs (see Appendix \ref{['sec:Q_construction']}). For reconfigurable converters, PowerGenie decouples the topology into single-mode sub-topologies and processes each independently.
• Figure 4: (a) PowerGenie-discovered best eight-mode power converter. Discovered control scheme is shown in Table \ref{['tab:8mode_control_powergenie']} (b) Analytical comparison: discovered-best achieves better SSL ($\tilde{M}_{\text{SSL}}$ = 0.732 vs. 0.642) with fewer capacitors ($\tilde{N}_{cap}$ = 0.417 vs. 0.458), while training-best shows better FSL ($\tilde{M}_{\text{FSL}}$ = 0.801 vs. 0.747). (c) SPICE results (TSMC 180 nm, $f_{\text{sw}}$ = 10 MHz, $C_{\text{total}}$ = 3 nF, 2% parasitic cap). Left: efficiency comparison at $I_{\text{out}}$ = 0.5 mA aligns with SSL metrics, indicating capacitor loss dominance. Right: average absolute efficiency gain of discovered topologies increases with load (reaching $10.45\%$ at 3 mA), demonstrating superior power handling capability.
• Figure 5: (a) A switch (NMOS transistor NM1) with 16-bit control scheme 0001010100101010 specifying on/off states across 8 modes and 2 phases. (b) Graph representation: device pins (NM1D, NM1G, NM1S, NM1B) form a cycle, and the gate node connects to VCONT nodes at active bit positions (2, 4, 6, 8, 10, 12, 15). This decomposition reduces tokenizer complexity from $2^{16} = 65{,}536$ to just 16 tokens while preserving full control scheme expressiveness.

Theorems & Definitions (20)

• Definition 3.3: Fundamental Loop Matrix, chua1987linear
• Definition 3.4: Fundamental Cutset Matrix, chua1987linear
• Definition 3.5: Properly Posed, seeman2009design
• Theorem 3.6: Properly Posed Criterion, seeman2009design
• Theorem 3.7: VCR Extraction, makowski1995performance
• Theorem 3.8: SSL Metric, seeman2008analysis
• Theorem 3.9: FSL Metric, seeman2008analysis
• Theorem 1.1: Properly Posed Criterion, seeman2009design
• proof
• Theorem 1.2: VCR Extraction, makowski1995performance