A Time-Domain Dual-Edge Asynchronous Pipelined SAR ADC Featuring Reset-Free Quantization at Multi-GS/s

TL;DR

The paper addresses the efficiency limits of high-speed time-domain ADCs by introducing dual-edge reset-free quantization in an asynchronous pipelined SAR architecture, enabling both rising and falling edges to carry information within a single conversion period. It details a 8-bit, 22-nm FD-SOI prototype with a linearity-compensated dual-edge VTC and a dual-edge TDC featuring decoupled delay units, achieving continuous 3.5 GS/s operation with SNDR 21.6 dB and SFDR 32.2 dB. The approach extends the usable conversion window and reduces reset overhead, with power scaling that remains favorable as speed increases (e.g., energy per sample ~6.35 pJ at 10.5 GS/s). The results demonstrate feasibility and scalability of reset-free dual-edge quantization for high-speed time-domain ADCs, with implementation-level refinements expected to unlock higher SNDR and broader adoption in next-generation wireline receivers.

Abstract

Time-domain ADCs are attractive for high-speed wireline receivers, as time resolution scales favorably with advanced CMOS technologies, enabling multi-GS/s single-channel sampling rates. However, conventional time-domain ADCs require explicit reset of voltage-to-time and time-domain signal paths between samples, introducing dead time that fundamentally limits resolution, speed, and energy efficiency. This paper introduces a dual-edge reset-free quantization concept for asynchronous pipelined SAR time-domain ADCs, in which both rising and falling signal edges are exploited to enable reset-free quantization within a single conversion period. By eliminating explicit reset phases, the proposed approach expands the effective conversion window and relaxes the resolution-speed tradeoff at high sampling rates. An 8-bit dual-edge asynchronous pipelined SAR time-domain ADC is implemented in 22-nm FD-SOI, incorporating a linearity-compensated dual-edge voltage-to-time converter and a dual-edge time-to-digital converter with independently tunable rising- and falling-edge delays. The prototype occupies a core area of 0.0089 mm^2 and achieves continuous single-channel operation at 3.5 GS/s, with architectural scalability demonstrated through intermittent operation at 10.5 GS/s and higher. At 3.5 GS/s, the ADC achieves 21.6 dB SNDR and 32.2 dB SFDR. The measured performance is primarily limited by identifiable implementation-level factors rather than by architectural constraints, demonstrating the feasibility of dual-edge reset-free quantization for high-speed time-domain ADCs.

Figures (16)

• Figure 1: Comparison between (a) conventional single-edge and (b) the proposed dual-edge quantization scheme.
• Figure 2: A high-level block diagram of the proposed time-domain dual-edge asynchronous pipelined SAR ADC.
• Figure 3: (a) Schematic of the proposed dual-edge VTC and the (b) post-layout simulation results at 12.5 GS/s illustrating the linearity compensation.
• Figure 4: (a) Simplified block diagram of the proposed TDC featuring dual-edge time comparison through asynchronous SAR operation. (b) Simplified timing diagram of the first two TDC stages illustrating the independent rising- and falling-edge decoupled pulse width adjustment. (c) Output bits synchronization scheme with two DFF banks.
• Figure 5: The circuit implementation of the proposed dual-edge time comparator.