NEXUS: Bit-Exact ANN-to-SNN Equivalence via Neuromorphic Gate Circuits with Surrogate-Free Training

TL;DR

NEXUS presents a radical shift in neuromorphic computing by constructing all IEEE-754 FP32 arithmetic from Integrate-and-Fire neuron gates and mapping FP32 values to 32 parallel spikes via Spatial Bit Encoding. This yields bit-exact ANN-to-SNN equivalence, allowing surrogate-free training since the forward pass is mathematically identical to the ANN. Empirical results across large language models and transformer blocks show identical task accuracy to ANN baselines with mean ULP errors around 6 and minimal 0-ULP occurrences, while achieving 27–168,000× energy reductions on Loihi 2 hardware. The single-timestep, leakage-immune encoding and robustness to realistic synaptic noise and threshold variations demonstrate practical viability for deployable, energy-efficient SNNs that do not sacrifice accuracy. Overall, NEXUS enables exact, efficient, and robust neuromorphic computation aligned with conventional floating-point standards.

Abstract

Spiking Neural Networks (SNNs) promise energy-efficient computing through event-driven sparsity, yet all existing approaches sacrifice accuracy by approximating continuous values with discrete spikes. We propose NEXUS, a framework that achieves bit-exact ANN-to-SNN equivalence -- not approximate, but mathematically identical outputs. Our key insight is constructing all arithmetic operations, both linear and nonlinear, from pure IF neuron logic gates that implement IEEE-754 compliant floating-point arithmetic. Through spatial bit encoding (zero encoding error by construction), hierarchical neuromorphic gate circuits (from basic logic gates to complete transformer layers), and surrogate-free STE training (exact identity mapping rather than heuristic approximation), NEXUS produces outputs identical to standard ANNs up to machine precision. Experiments on models up to LLaMA-2 70B demonstrate identical task accuracy (0.00\% degradation) with mean ULP error of only 6.19, while achieving 27-168,000$\times$ energy reduction on neuromorphic hardware. Crucially, spatial bit encoding's single-timestep design renders the framework inherently immune to membrane potential leakage (100\% accuracy across all decay factors $β\in[0.1,1.0]$), while tolerating synaptic noise up to $σ=0.2$ with >98\% gate-level accuracy.

Figures (5)

• Figure 1: Comparison of spike encoding schemes.(Left) Traditional Temporal Encoding (e.g., Rate Coding): Relies on stochastic spike statistics over long time windows (e.g., 1024 time steps) to approximate continuous values, inherently introducing approximation errors with high latency. (Right) Spatial Bit Encoding (Ours): Operates within a fixed short window ($N$ steps, e.g., 32 for FP32). Through deterministic bit extraction with dynamic threshold $\Theta(t)$, each IEEE-754 bit is precisely extracted at specific time steps, establishing a lossless bijection between input values and spike sequences with zero encoding error.
• Figure 2: Hierarchical architecture of neuromorphic gate circuits with surrogate-free backpropagation.Forward Pass (blue upward path): Bottom-up construction from IF neurons to complex nonlinear functions. Level 1-2: IF neurons implement logic primitives (AND, OR, NOT) and bit-level full adders. Level 3: Cascaded construction of IEEE-754 compliant FP32 arithmetic pipelines (adder, multiplier, divider). Level 4: Nonlinear functions (Softmax, SiLU, etc.) decomposed into exact FP32 operation sequences, ensuring bit-exact forward computation. Backward Pass (red downward path): Surrogate-free backpropagation mechanism. Since forward computation is mathematically equivalent to ANN (no quantization error), the Straight-Through Estimator (STE) becomes an exact identity mapping ($\frac{\partial S}{\partial x} = 1$) rather than a heuristic approximation. Gradients ($\frac{\partial \mathcal{L}}{\partial S}$) flow directly through bit-exact modules without requiring smooth surrogate functions.
• Figure 3: LIF decay factor robustness: accuracy vs. $\beta$ for logic gates and arithmetic units. All components maintain 100% accuracy across the entire range, confirming inherent immunity to membrane leakage.
• Figure 4: Input noise robustness: (a) logic gates maintain ${>}98\%$ accuracy at $\sigma \leq 0.2$; (b) arithmetic units degrade faster due to carry-chain error propagation.
• Figure 5: Floating-point operator robustness under input noise. Lower-precision formats (FP8) are more robust than higher-precision formats (FP32), as fewer bits are susceptible to noise-induced flips.

Theorems & Definitions (3)

• Theorem 1.1: Lossless Bijection
• proof
• Corollary 1.2: Zero Encoding Error