FireFly-P: FPGA-Accelerated Spiking Neural Network Plasticity for Robust Adaptive Control

TL;DR

FireFly-P addresses real-time adaptive control by coupling spiking neural network plasticity with FPGA acceleration. It introduces an offline evolutionary-strategy–driven rule for synaptic updates and an online, dual-engine hardware core that performs inference and weight adaptation in a tightly synchronized pipeline. The approach delivers end-to-end latency of 8 μs, consumes 0.713 W, and uses ~10K LUTs on an Artix-7 FPGA, enabling robust generalization in dynamic environments and edge robotics tasks. This work demonstrates the viability of hardware-accelerated SNN plasticity for low-power, low-latency autonomous control with online learning capabilities.

Abstract

Spiking Neural Networks (SNNs) offer a biologically plausible learning mechanism through synaptic plasticity, enabling unsupervised adaptation without the computational overhead of backpropagation. To harness this capability for robotics, this paper presents FireFly-P, an FPGA-based hardware accelerator that implements a novel plasticity algorithm for real-time adaptive control. By leveraging on-chip plasticity, our architecture enhances the network's generalization, ensuring robust performance in dynamic and unstructured environments. The hardware design achieves an end-to-end latency of just 8~$μ$s for both inference and plasticity updates, enabling rapid adaptation to unseen scenarios. Implemented on a tiny Cmod A7-35T FPGA, FireFly-P consumes only 0.713~W and $\sim$10K~LUTs, making it ideal for power- and resource-constrained embedded robotic platforms. This work demonstrates that hardware-accelerated SNN plasticity is a viable path toward enabling adaptive, low-latency, and energy-efficient control systems.

Figures (4)

• Figure 1: The FireFly-P framework pipeline. Plasticity parameters are first optimized in an offline stage. Subsequently, the learned rule is deployed on a dual-engine FPGA accelerator for online, real-time adaptive control.
• Figure 2: The FireFly-P hardware architecture, featuring a Dual-Engine Computation Core (Forward Engine for inference, Plasticity Engine for weight updates), a Scheduler, and an On-Chip Memory System, where multi-level pipelining is used to hide latency between the engines and across layers.
• Figure 3: Performance of FireFly-P vs. weight-trained SNNs on three continuous control tasks, where FireFly-P adapts faster and achieves higher performance.
• Figure 4: Implemented design layout of FireFly-P on a Xilinx Artix-7 FPGA.