The First Switch Effect in Ferroelectric Field-Effect Transistors

TL;DR

The paper tackles the limited write endurance of ferroelectric field-effect transistors (FEFETs) by introducing the First Switch Effect as the dominant early degradation mechanism. By comparing FEFETs to an equivalent MOSFET with the same $EOT$ and using stepwise polarization, PUND, and frequency-dependent charge pumping, it shows that the initial write pulse creates a large density of interfacial traps near the Si/SiO2 interface, contributing up to about $90\%$ of total defect density under unipolar stress and about $50\%$ under bipolar stress before memory window closure. Continued bipolar cycling then generates additional traps both at the interface and deeper in the gate stack, which contrasts with MOSFETs where damage remains largely at the interface. The findings highlight the critical role of the first switch in FEFET reliability and point to targeted mitigation of early interfacial trapping as a route to improving endurance in ferroelectric memories.

Abstract

In this work, a ferroelectric field-effect transistor (FEFET) is systematically characterized and compared with an equivalent standard MOSFET with an equivalent oxide thickness. We show that these two devices, with a silicon channel, exhibit similar pristine state transfer characteristics but starkly different endurance characteristics. In contrast to the MOSFET, the FEFET shows a significant increase in sub-threshold swing in the first write pulse. Based on this, we reveal that this first write pulse (cycle 1) generates more than half of the total traps generated during the fatigue cycling in FEFETs. We call this the 'First Switch Effect'. Further, by polarizing a pristine FEFET step by step, we demonstrate a direct correlation between the switched polarization and interface trap density during the first switch. Through charge pumping measurements, we also observe that continued cycling generates traps more towards the bulk of the stack, away from the Si/SiO2 interface in FEFETs. We establish that: (1) the first switch effect leads to approximately 50% of the total trap density (Nit) near the Si/SiO2 interface until memory window closure; and (2) further bipolar cycling leads to trap generation both at and away from Si/SiO2 interface in FEFETs.

Figures (8)

• Figure 1: Schematic showing the first switch and cycling degradation stages in FEFETs.
• Figure 2: Process flow and STEM image of crystalline FE-HZO FET and amorphous dielectric HZO FET. Diffraction patterns confirm the crystallinity and amorphous nature of FEFET and MOSFET respectively.
• Figure 3: a,b) C-V curves showing the same effective oxide thickness (EOT) for both devices c,d) PV loops measured for the MOSFET and FEFET. The FEFET shows a clear hysteresis loop while the MOSFET shows a dielectric response.
• Figure 4: a,b) I$_d$-V$_g$ curves for the MOSFET and FEFET. b,c) Memory window vs voltage curves for the MOSFET and FEFET. The FEFET shows a maximum memory window of 1.5 V at a program voltage of 3.5 V while the MOSFET does not show any memory window.
• Figure 5: Measurement scheme for unipolar and bipolar measurements in these devices. b) $I_d-V_g$ for the FEFET under bipolar stress, unipolar stress and MOSFET under bipolar stress respectively. c) $V_T$ shift with cycles for pristine and post first switch cases. d) Change in subthreshold swing with cycles.