Snowball: A Scalable All-to-All Ising Machine with Dual-Mode Markov Chain Monte Carlo Spin Selection and Asynchronous Spin Updates for Fast Combinatorial Optimization

TL;DR

Snowball tackles the challenge of scalable, fast combinatorial optimization by deploying a digital, all-to-all Ising machine with dual-mode Markov chain Monte Carlo spin selection and asynchronous updates on FPGA hardware. It combines a bit-plane representation of couplings, incremental local-field updates, and a piecewise-linear exponential approximation to implement high-precision, fast Ising dynamics with two actionable spin-update modes (random-scan and roulette-wheel) under simulated annealing. The architecture achieves substantial improvements in time-to-solution on both sparse (Gset) and dense ($K_{2000}$) Max-Cut benchmarks, including up to an 8× speedup over prior Ising machines and dramatic gains over exact baselines, while maintaining competitive solution quality. This work demonstrates a practical path to high-precision, scalable Ising computation for real-world dense optimization problems on FPGA platforms, with implications for accelerated combinatorial optimization.

Abstract

Ising machines have emerged as accelerators for combinatorial optimization. To enable practical deployment, this work aims to reduce time-to-solution by addressing three challenges: (1) hardware topology, (2) spin selection and update algorithms, and (3) scalable coupling-coefficient precision. Restricted topologies require minor embedding; naive parallel updates can oscillate or stall; and limited precision can preclude feasible mappings or degrade solution quality. This work presents Snowball, a digital, scalable, all-to-all coupled Ising machine that integrates dual-mode Markov chain Monte Carlo spin selection with asynchronous spin updates to promote convergence and reduce time-to-solution. The digital architecture supports wide, configurable coupling precision, unlike many analog realizations at high bit widths. A prototype on an AMD Alveo U250 accelerator card achieves an 8$\times$ reduction in time-to-solution relative to a state-of-the-art Ising machine on the same benchmark instance.

Figures (15)

• Figure 1: Illustration of a cut induced by $S\subseteq V$. Dashed edges form the cutset $\delta(S)$; their weights sum to the cut weight $w(\delta(S))$.
• Figure 2: (a) Fully connected five-spin Ising model on the complete graph $K_5$ with pairwise couplings $J_{ij}$ and site-dependent external fields $h_i$. (b) The Ising Hamiltonian is shown over all $2^5$ spin configurations $\mathbf{s}\in\{\pm 1\}^5$.
• Figure 3: Glauber flip probability $P_{\mathrm{flip}}$ versus energy change $\Delta E$. As $T\to\infty$, $P_{\mathrm{flip}}\to 0.5$ (flips are effectively random). As $T\to 0^+$, $P_{\mathrm{flip}}\to 1$ for $\Delta E<0$, $P_{\mathrm{flip}}\to 0.5$ for $\Delta E=0$, and $P_{\mathrm{flip}}\to 0$ for $\Delta E>0$—i.e., only energy-decreasing flips are accepted.
• Figure 4: Example run on a Max-Cut instance solved via simulated annealing. (a) Under linear cooling, $H(\mathbf{s})$ decreases overall as $T$ decreases. (b) Spin configurations on a 2D grid at checkpoints [A]--[F] with their $T$ and $H(\mathbf{s})$ values. At [F], the system attains the ground-state configuration "ISCA26".
• Figure 5: Illustration of a minor embedding. (a) Problem graph: complete graph $K_6$ with six logical spins. (b) Corresponding embedding on the Chimera hardware topology dwave_qpu, requiring more than six physical spins because the hardware connectivity is sparser than that of the problem graph.