Echo Cross Resonance gate error budgeting on a superconducting quantum processor

TL;DR

This work tackles gate fidelity variability on a medium-scale superconducting QPU by developing an error-budgeting workflow for the native echo cross-resonance (ECR) two-qubit gate on the Toshiko Gen-1 device. It decomposes the total gate error into incoherent ($T_1$, $T_2$-related) decoherence, control leakage, and coherent terms ($IZ$, $ZZ$), and applies hardware-free suppression via DRAG pulse shaping, compensating virtual-Z rotations, and ZZ-cancellation techniques. Across a connected 16-qubit chain, the median interleaved RB error per gate drops from about 4.6% to 1.2%, with the largest gains on previously weak links, demonstrating practical suppression of the low-performing tail. The results show that such error budgeting can be folded into routine calibration to inform device design and scalability, reducing the need for extra hardware while guiding speed-vs-coherence trade-offs for future quantum processors.

Abstract

High fidelity quantum operations are key to enabling fault-tolerant quantum computation. Superconducting quantum processors have demonstrated high-fidelity operations, but on larger devices there is commonly a broad distribution of qualities, with the low-performing tail affecting near-term performance and applications. Here we present an error budgeting procedure for the native two-qubit operation on a 32-qubit superconducting-qubit-based quantum computer, the OQC Toshiko gen-1 system. We estimate the prevalence of different forms of error such as coherent error and control qubit leakage, then apply error suppression strategies based on the most significant sources of error, making use of pulse-shaping and additional compensating gates. These techniques require no additional hardware overhead and little additional calibration, making them suitable for routine adoption. An average reduction of 3.7x in error rate for two qubit operations is shown across a chain of 16 qubits, with the median error rate improving from 4.6$\%$ to 1.2$\%$ as measured by interleaved randomized benchmarking. The largest improvements are seen on previously under-performing qubit pairs, demonstrating the importance of practical error suppression in reducing the low-performing tail of gate qualities and achieving consistently good performance across a device.

Figures (5)

• Figure 1: (Left) Photograph of a Toshiko QPU chip in an open sample package. 35 coaxmon qubits and 8 through-sapphire metal pillars are visible. (Right) Illustration of the qubit connectivity for Toshiko Tokyo-1. The pairs of qubits that were benchmarked are numbered for reference in later figures, while unused qubits and connections are shown grayed out.
• Figure 2: Control qubit leakage errors. (a) Illustrates the different leakage types occurring between energy levels. (b) Shows the circuit used to amplify and assess leakage errors, consisting of a repeat unit of a $ZX(\pi/4)$ pulse and a $Z(\phi)$ rotation. The angle $\phi$ is swept to locate an angle where the leakage errors add coherently, resulting in error amplification. (c) Leakage error suppression is achieved by modifying the pulse shape using DRAG. The original pulse shape (purple line) is supplemented by its derivative added in the quadrature $Q$ (green line), multiplied by some DRAG parameter. Representative results from the error amplification circuit are shown for pairs exhibiting (d) $\Lambda_{01}$, (e) $\Lambda_{12}$, and (f) $\Lambda_{02/2}$ type leakage. The upper and lower lines correspond to the control qubit being initially prepared in $\ket{0}$ or $\ket{1}$ state, respectively. Dashed and solid lines show the results before and after leakage suppression.
• Figure 3: Qubit rotation and pulse level views of the ECR gate. a) - the naive implementation of the ECR, consisting of $ZX(\pi/4)$, $X$, and $ZX(-\pi/4)$ rotations. At the pulse level, the $X$ gate is implemented as two $SX$ rotations, each a Gaussian pulse with DRAG, which is the native one-qubit gate on Toshiko. b) - the ECR gate with corrections for coherent error, including $RZ$ and $RY$ rotations on the target qubit before and after each $ZX(\pi/4)$.
• Figure 4: Error budget, showing the error-per-gate coming from incoherent errors, $\hat{IZ}$ and $\hat{ZZ}$ coherent errors, and control leakage errors. For each qubit pair the errors before/after the application of error suppression are shown on the left/right.
• Figure 5: Comparison of interleaved benchmarking before and after error-suppression. Cumulative distributions of measured EPG over the separate qubit pairs. Dashed lines show the respective mean values.