Primitive-Driven Acceleration of Hyperdimensional Computing for Real-Time Image Classification

TL;DR

This work addresses the real-time image classification bottleneck in hyperdimensional computing (HDC) by introducing a patch-based, spatially aware image encoder and an end-to-end FPGA accelerator. The encoder maps local image patches into hypervectors using position- and intensity-dependent banks, then aggregates them with permutation and bundling to form a global representation, achieving strong MNIST and Fashion-MNIST accuracy. The FPGA design implements the full inference pipeline as a streaming dataflow engine with a patch processor array, global adder tree, and similarity engine, delivering sub-millisecond latency and up to 1300x/60x speedups over CPU/GPU baselines, respectively. Ablation studies validate the chosen patch size and hypervector dimension ($3\\times3$, $D=10{,}000$) and demonstrate gains from online similarity-guided updates, highlighting the practical potential of low-power, hardware-friendly HDC for real-time imaging tasks.

Abstract

Hyperdimensional Computing (HDC) represents data using extremely high-dimensional, low-precision vectors, termed hypervectors (HVs), and performs learning and inference through lightweight, noise-tolerant operations. However, the high dimensionality, sparsity, and repeated data movement involved in HDC make these computations difficult to accelerate efficiently on conventional processors. As a result, executing core HDC operations: binding, permutation, bundling, and similarity search: on CPUs or GPUs often leads to suboptimal utilization, memory bottlenecks, and limits on real-time performance. In this paper, our contributions are two-fold. First, we develop an image-encoding algorithm that, similar in spirit to convolutional neural networks, maps local image patches to hypervectors enriched with spatial information. These patch-level hypervectors are then merged into a global representation using the fundamental HDC operations, enabling spatially sensitive and robust image encoding. This encoder achieves 95.67% accuracy on MNIST and 85.14% on Fashion-MNIST, outperforming prior HDC-based image encoders. Second, we design an end-to-end accelerator that implements these compute operations on an FPGA through a pipelined architecture that exploits parallelism both across the hypervector dimensionality and across the set of image patches. Our Alveo U280 implementation delivers 0.09ms inference latency, achieving up to 1300x and 60x speedup over state-of-the-art CPU and GPU baselines, respectively.

Figures (4)

• Figure 1: Overall patch-based HDC encoding pipeline (during inference).
• Figure 2: Overview of the proposed primitive-driven HDC acceleration framework. (a) The accelerator architecture exposes both patch-level and hypervector-level parallelism using multiple patch processors, a global adder tree, a similarity engine, and a lightweight argmax unit. (b) End-to-end system mapping from the patch-based encoding algorithm to FPGA compute kernels and host–device execution flow.
• Figure 3: Latency and throughput speedup relative to the CPU baseline. (Top) Effects of patch size using $D{=}10{,}000$. (Bottom) Scaling with hypervector dimension $D$. CPU speedup baseline is $1\times$.
• Figure 4: Effect of patch size and hypervector dimension on MNIST accuracy. Results are shown for both single-pass training and OnlineHD-style retraining. Smaller patches preserve discriminative structure, and accuracy improves with larger $D$ but saturates beyond $10{,}000$.