Understanding Bottlenecks for Efficiently Serving LLM Inference With KV Offloading
William Meng, Benjamin Lee, Hong Wang
TL;DR
This work analyzes KV cache offloading for long-context LLM inference and identifies a fundamental memory-bound bottleneck driven by CPU-GPU PCIe bandwidth. By deriving the critical ratio $κ_{ ext{crit}}$ and the workload ratio $κ_{ ext{ratio}}$, the authors predict when prefill shifts from compute- to memory-bound regimes and validate these insights with extensive experiments across model types and hardware platforms. They find that real workloads routinely operate well into the memory-bound region (often with up to 99% of time spent on transfers) and that GPUs run far below peak TDP, highlighting inefficiencies in current serving stacks. The paper then proposes a set of hardware, model-architecture, and workload-aware scheduling optimizations—such as MLA-based KV compression, NVLink/HBM integrations, and utilization-aware scheduling—to extend the compute-bound regime and improve overall latency and throughput for KV offloaded inference.
Abstract
KV cache offloading enables long-context LLM inference by storing caches in CPU DRAM, but PCIe bandwidth limitations create severe bottlenecks. In this paper, we develops an analytical framework that derives $κ_{\text{crit}}$, the critical cached-to-prefill token ratio where execution becomes memory-bound and show typical workloads exceed this threshold by orders of magnitude. Empirical characterization reveals 99\% of latency spent on transfers and serving offloaded requests results in GPU's consuming only 28\% of their rated TDP, motivating our proposed optimizations for hardware interconnects, model architectures, and scheduling algorithms.
