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A Cache-Aware Hybrid Sieve Combining Segmentation and Bit-Packing for Fast Prime Generation

Kathi Lakshmi Mani Thirdhana

TL;DR

The paper tackles slow prime generation on modern CPUs caused by memory hierarchy bottlenecks in the classical sieve. It introduces a cache-aware hybrid sieve that segments the range into cache-sized blocks, stores only odd numbers with 1 bit per value, and aligns blocks to cache lines, while reusing primes up to $\sqrt{N}$. Empirical results up to $N=10^9$ show up to $2.4\times$ faster runtimes and $8\times$ lower memory usage compared to the classical sieve, illustrating substantial practical gains from architecture-aware design. The work provides a memory-access model, discusses scalability, and outlines extensibility avenues like SIMD, wheel factorization, and parallel implementations for massive-scale prime generation.

Abstract

Prime generation is a fundamental task in cryptography, number theory, and randomized algorithms. While the classical Sieve of Eratosthenes is simple and efficient in theory, its practical performance on modern central processing units is often limited by memory access inefficiencies. This paper introduces a cache-aware hybrid sieve that integrates segmentation, bit-packing, and cache-line-aligned block processing to optimize memory bandwidth and level one and level two cache locality. The proposed approach reduces memory usage by storing only odd numbers and using one bit per value. The sieve range is divided into cache-sized blocks to minimize cache misses, while primes up to the square root of the limit are reused across blocks. Experimental results demonstrate up to an eight times reduction in memory usage and runtime improvements of up to two point four times compared to the classical sieve and one point seven times compared to the segmented sieve. Benchmarks up to ten to the power of nine illustrate that architecture-aware algorithm design can yield substantial practical performance gains.

A Cache-Aware Hybrid Sieve Combining Segmentation and Bit-Packing for Fast Prime Generation

TL;DR

The paper tackles slow prime generation on modern CPUs caused by memory hierarchy bottlenecks in the classical sieve. It introduces a cache-aware hybrid sieve that segments the range into cache-sized blocks, stores only odd numbers with 1 bit per value, and aligns blocks to cache lines, while reusing primes up to . Empirical results up to show up to faster runtimes and lower memory usage compared to the classical sieve, illustrating substantial practical gains from architecture-aware design. The work provides a memory-access model, discusses scalability, and outlines extensibility avenues like SIMD, wheel factorization, and parallel implementations for massive-scale prime generation.

Abstract

Prime generation is a fundamental task in cryptography, number theory, and randomized algorithms. While the classical Sieve of Eratosthenes is simple and efficient in theory, its practical performance on modern central processing units is often limited by memory access inefficiencies. This paper introduces a cache-aware hybrid sieve that integrates segmentation, bit-packing, and cache-line-aligned block processing to optimize memory bandwidth and level one and level two cache locality. The proposed approach reduces memory usage by storing only odd numbers and using one bit per value. The sieve range is divided into cache-sized blocks to minimize cache misses, while primes up to the square root of the limit are reused across blocks. Experimental results demonstrate up to an eight times reduction in memory usage and runtime improvements of up to two point four times compared to the classical sieve and one point seven times compared to the segmented sieve. Benchmarks up to ten to the power of nine illustrate that architecture-aware algorithm design can yield substantial practical performance gains.
Paper Structure (13 sections, 2 figures, 2 tables, 1 algorithm)

This paper contains 13 sections, 2 figures, 2 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Related Work
  3. Cache-Aware Hybrid Sieve
  4. Block Design
  5. Algorithm
  6. Memory-Access Model
  7. Experimental Setup
  8. Performance Results
  9. Runtime Table
  10. Runtime Plot
  11. Speedup Plot
  12. Discussion
  13. Conclusion

Figures (2)

  • Figure 1: Runtime vs $N$. The hybrid sieve scales efficiently due to better cache locality and reduced memory footprint.
  • Figure 2: Speedup vs Hybrid Sieve. The hybrid sieve demonstrates increasing advantage as $N$ grows due to reduced cache misses and memory traffic.