GTAC: A Generative Transformer for Approximate Circuits

TL;DR

GTAC introduces a Generative Transformer approach to Approximate Logic Synthesis by directly generating approximate circuits within a user-specified error bound $\epsilon$. It combines sequential DAG-to-token encoding, an error-tolerant masking mechanism, and a hybrid training regime (supervised pretraining plus RL fine-tuning) with iterative self-evolution and MCTS-based inference to explore Pareto-optimal designs. The method achieves notable improvements in area and delay under the error constraint while offering substantial speedups compared to prior ALS methods, demonstrating the viability of transformer-based constrained generation for error-resilient circuit design. The work advances practical AI-driven EDA by enabling larger design spaces, explicit PPA-error trade-offs, and scalable optimization on realistic benchmarks like IWLS."

Abstract

Targeting error-tolerant applications, approximate circuits introduce controlled errors to significantly improve performance, power, and area (PPA) of circuits. In this work, we introduce GTAC, a novel generative Transformer-based model for producing approximate circuits. By leveraging principles of approximate computing and AI-driven EDA, our model innovatively integrates error thresholds into the design process. Experimental results show that compared with a state-of-the-art method, GTAC further reduces 6.4% area under the error rate constraint, while being 4.3x faster.

Figures (6)

• Figure 1: Comparison between (a) the exact logic synthesis and (b) the approximate logic synthesis using Transformer, which need 5 and 3 generation steps, respectively.
• Figure 2: Illustration of "unfolding" a DAG with a multi-fanout node ($n_1$). A depth-first traversal starting from $g_1$ might produce $s_{g1} = [\text{AND}, x_1, n_1]$. The traversal for $g_2$ would then produce $s_{g2} = [\text{AND}, n_1, x_5]$. The final "unfolded" sequence $s = [s_{g1}, s_{g2}]$ generates the sub-graph for $n_1$ twice.
• Figure 3: Overview of GTAC model. (a) Training: The model takes as inputs a circuit pair comprising the exact circuit and its ground-truth approximate circuit and learns to generate its approximate variants by minimizing a multi-objective loss (size and error). (b) Inference: For a new target circuit and error bound $\epsilon$, it generates a approximate circuit, with error-tolerant masking ensuring the output satisfies $\mathcal{E}(g, f) \leq \epsilon$.
• Figure 4: The GTAC pipeline has two stages. In the Training phase, the model learns a supervised mapping from exact to approximate circuits. In the Improvement phase, sampled circuits are refined via approximate synthesis, and the fine-tuned Transformer with MCTS generates new candidates; high-quality pairs are added for iterative self-improvement.
• Figure 5: Pareto front of the evaluated design cases: (a) Error rate versus delay; (b) Error rate versus area.