Flexible Bit-Truncation Memory for Approximate Applications on the Edge

TL;DR

The paper tackles the challenge of enabling runtime quality-power adaptation for data-intensive edge applications by introducing TrunMem, a flexible bit-truncation memory. It provides a complete hardware design with truncation-manager arrays, power-gating, and both byte and word modes, enabling truncation from 0 to 32 bits and supporting multiple domains such as video storage and DNN weight storage. A mathematical result yields the optimal dummy values for truncated bits in floating-point representations, and the authors present a full-chip implementation with post-layout verification demonstrating substantial power savings (up to 47.02% in video and 51.69% in DNN inference) at a modest area overhead (2.89%). Evaluations across 4,525 videos and multiple DNN tasks show that runtime truncation can complement software compression techniques to enhance edge deployment, with open-source emulators provided for reproducibility. The work suggests broad applicability beyond video and DNNs, offering a general approach to adaptive memory for power-efficient edge computing.

Abstract

Bit truncation has demonstrated great potential to enable run-time quality-power adaptive data storage, thereby optimizing the power/energy efficiency of approximate applications and supporting their deployment in edge environments. However, existing bit-truncation memories require custom designs for a specific application. In this paper, we present a novel bit-truncation memory with full adaptation flexibility, which can truncate any number of data bits at run time to meet different quality and power trade-off requirements for various approximate applications. The developed bit-truncation memory has been applied to two representative data-intensive approximate applications: video processing and deep learning. Our experiments show that the proposed memory can support three different video applications (including luminance-aware, content-aware, and region-of-interest-aware) with enhanced power efficiency (up to 47.02% power savings) as compared to state-of-the-art. In addition, the proposed memory achieves significant (up to 51.69%) power savings for both baseline and pruned lightweight deep learning models, respectively, with a low implementation cost (2.89% silicon area overhead).

Figures (11)

• Figure 1: Bit truncation for viewer-aware video storage.
• Figure 2: TrunMEM enabled software-hardware co-design for edge intelligence.
• Figure 3: Proposed TrunMEM: (a) Memory structure and (b) Truncation manager circuitry and truth table. The components found within the Precharge, SRAM arrays, Row decoder & driver, write driver, and sense amplifier are typical components found within common SRAM. The Truncation Managers are responsible for controlling the state of the data type (32bit float, or 8bit integer).
• Figure 4: Timing diagram of TrunMEM. At byte mode, the binary value "010101...01" is written to a random word, followed by four reading operations (starting with normal reading, 2-bit truncation, 3-bit truncation, and 4-bit truncation). Similarly, with the byte mode disabled, i.e., at the word mode, the value is written, followed by reads at 0-bit, 2-bit, 3-bit and 16-bit truncation.
• Figure 5: Power consumption of TrunMEM at each level of bit truncation on a 32x1024 memory array. Using Xscheme Xschem, NGspice NGspice, and the Sky130 PDK sky130

Theorems & Definitions (2)

• Proposition 1
• proof