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A Folded Surface Code Architecture for 2D Quantum Hardware

Zhu Sun, Zhenyu Cai

TL;DR

This work tackles scaling fault-tolerant quantum computation on strictly 2D hardware by using looped pipelines to realize quasi-3D connectivity and folding rotated surface codes. It shows how folded surface codes enable transversal Clifford gates with constant-time runtimes within a stack and leverages a transversal $S$ gate to dramatically reduce the spacetime volume of 8T-to-CCZ magic-state distillation, achieving improvements over standard 2D lattice surgery and prior looped designs. The authors provide explicit intra-loop and transversal-gate protocols, concrete timing formulas, and a silicon-qubit instantiation demonstrating practical cycle times, along with a virtual-stack architecture that enables multilayer routing and improved parallelism. These advances yield substantial resource efficiency and scalability for large-scale fault-tolerant quantum computation on 2D hardware, with clear paths for compiler optimization and refined distillation protocols in future work.

Abstract

Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from $\mathcal{O}(d)$ in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal $S$ gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.

A Folded Surface Code Architecture for 2D Quantum Hardware

TL;DR

This work tackles scaling fault-tolerant quantum computation on strictly 2D hardware by using looped pipelines to realize quasi-3D connectivity and folding rotated surface codes. It shows how folded surface codes enable transversal Clifford gates with constant-time runtimes within a stack and leverages a transversal gate to dramatically reduce the spacetime volume of 8T-to-CCZ magic-state distillation, achieving improvements over standard 2D lattice surgery and prior looped designs. The authors provide explicit intra-loop and transversal-gate protocols, concrete timing formulas, and a silicon-qubit instantiation demonstrating practical cycle times, along with a virtual-stack architecture that enables multilayer routing and improved parallelism. These advances yield substantial resource efficiency and scalability for large-scale fault-tolerant quantum computation on 2D hardware, with clear paths for compiler optimization and refined distillation protocols in future work.

Abstract

Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.
Paper Structure (20 sections, 9 equations, 16 figures, 1 table)

This paper contains 20 sections, 9 equations, 16 figures, 1 table.

Table of Contents

  1. Introduction
  2. Background
  3. Surface codes and their variants
  4. Standard looped pipeline architecture
  5. intra-loop interactions
  6. looped pipeline with folded surface code
  7. General Implementation
  8. Example: Silicon Spin Qubits
  9. Magic State Factory
  10. virtual stack architecture
  11. Conclusion
  12. Protocol Runtimes
  13. Qubit rearrangement
  14. Stabiliser checks for folded surface code
  15. H, S and CNOT gate
  16. ...and 5 more sections

Figures (16)

  • Figure 1: A distance 3 rotated surface code patch and the corresponding folded patch.
  • Figure 2: $S$ gate implemented by Y basis measurement.
  • Figure 3: The looped pipeline architecture. By placing more qubits in each loop via pipelining, we can 'stack' the patches.
  • Figure 4: The hallway layout for stacks of logical qubits. Both data (purple) and ancilla (white) code patches are stored in stacks. While some intra-stack operations are transversal, inter-stack operations still require lattice surgery.
  • Figure 5: A stack of distance-3 surface code patches implemented using looped pipeline architecture.
  • ...and 11 more figures