DynQ: A Dynamic Topology-Agnostic Quantum Virtual Machine via Quality-Weighted Community Detection

TL;DR

DynQ is presented, the first dynamic, topology-agnostic Quantum Virtual Machine that virtualises quantum hardware using quality-weighted community detection and operationalises the classical virtualisation principle of high cohesion and low coupling in a quantum-native setting.

Abstract

Quantum cloud platforms remain fundamentally non-virtualised: despite rapid hardware scaling, each user program still monopolises an entire quantum processor, preventing resource sharing, economic scalability, and quality-of-service differentiation. Existing Quantum Virtual Machine (QVM) designs attempt spatial multiplexing through topology-specific or template-based partitioning, but these approaches are brittle under hardware heterogeneity, calibration drift, and transient defects, which dominate real quantum devices. We present DynQ, the first dynamic, topology-agnostic Quantum Virtual Machine that virtualises quantum hardware using quality-weighted community detection. Instead of imposing fixed geometric regions, DynQ models a quantum processor as a weighted graph derived from live calibration data and automatically discovers execution regions that maximise internal gate quality while minimising inter-region coupling. This operationalises the classical virtualisation principle of high cohesion and low coupling in a quantum-native setting, producing execution regions that are connectivity-efficient, noise-aware, and resilient to crosstalk and defects. We evaluate DynQ across five IBM Quantum backends using calibration-derived noise simulation and on two production devices, comparing against state-of-the-art QVM and standard compilation baselines. On hardware with pronounced spatial quality variation, DynQ achieves up to 19.1 percent higher fidelity and 45.1 percent lower output error. When transient hardware defects cause baseline executions to fail completely, DynQ adapts dynamically and achieves over 86 percent fidelity. By transforming calibrated device graphs into adaptive virtual hardware abstractions, DynQ decouples quantum programs from fragile physical layouts and enables reliable, high-utilisation quantum cloud services.

Figures (9)

• Figure 1: Representative coupling maps of superconducting quantum processors. Each node denotes a physical qubit, while edges indicate pairs of qubits supporting native two-qubit gates. The illustrated coupling graphs highlight the structural diversity and sparsity of contemporary superconducting hardware. (a) IBM Heron r3 series adopts a heavy-hex–inspired lattice with deliberately reduced connectivity to mitigate frequency collisions and crosstalk. (b) Rigetti Ankaa-3 follows a lattice-based layout with localised connectivity constraints. Despite differing geometric organisations, both architectures exhibit irregular and non-uniform coupling patterns, posing significant challenges for topology-aware quantum compilation and motivating the need for hardware-agnostic allocation and mapping strategies.
• Figure 2: The layered architecture of DynQ. The design explicitly decouples computationally intensive topology analysis (Offline Discovery Layer) from latency-critical scheduling decisions (Online Allocation Layer). By abstracting physical device properties into a HardwareGraph, the system maintains a pool of pre-validated QVM atomic regions to efficiently service incoming user programs.
• Figure 3: Visualisation of the offline discovery results on the 156-qubit IBM Kingston backend. The processor is partitioned into 15 disjoint QVM atomic regions with their corresponding score (coloured regions) by DynQ. Unlike rigid geometric partitioning, these irregular subgraphs naturally adapt to the heavy-hex topology and connectivity constraints, ensuring 100% hardware coverage as quantified in Table \ref{['tab:discovery']}.
• Figure 4: Performance characterisation of the DynQ compiler under noisy simulation across diverse backend topologies. (a) L1 Error Distribution: The Total Variation Distance (L1 Error) between the ideal and noisy output probability distributions. Lower values indicate higher simulation accuracy. DynQ (orange) consistently exhibits lower error rates compared to the default compiler (green) across all simulated chips. (b) Fidelity Distribution: Circuit fidelity scores for the same set of benchmarks. The dataset aggregates noisy simulations based on calibration profiles of 5 IBM Quantum backends (including Kingston and Torino). DynQ demonstrates higher median fidelity and lower performance variance, thereby mitigating noise-induced errors.
• Figure 5: Circuit-level performance analysis. (a) Distribution of fidelity improvement ($\Delta F$) across backends. The system shows high consistency on stable devices (Pittsburgh, Fez) while unlocking significant "high-reward" potential on noisy ones (Kingston). (b) Correlation between baseline fidelity and optimisation efficacy. The strong negative trend ($r \approx -0.53$) indicates that DynQ primarily aids low-fidelity circuits ($<0.6$) while having a neutral impact on high-fidelity ones ($>0.9$).