OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation

TL;DR

OSIRIS presents an end-to-end, parasitic-aware back-end framework for analog IC design that enables scalable ML research by generating large, annotated layout datasets and exploring layout space iteratively. It introduces two hierarchical design-space dimensions (finger permutations and component placement) and a two-stage pipeline (Fingers Permutation followed by Variants Generation) to produce thousands of DRC-clean, LVS-verified layouts. A two-level RL baseline guides exploration, improving parasitic-aware metrics (pex_score) and area while reducing search time. Beyond dataset generation, OSIRIS demonstrates a practical use case by fine-tuning an LLM to synthesize component layouts from sizing targets, achieving valid, manufacturable outputs. The work provides an open, extensible platform with significant implications for accelerating ML-driven back-end analog design and benchmarking.

Abstract

The automation of analog integrated circuit (IC) design remains a longstanding challenge, primarily due to the intricate interdependencies among physical layout, parasitic effects, and circuit-level performance. These interactions impose complex constraints that are difficult to accurately capture and optimize using conventional design methodologies. Although recent advances in machine learning (ML) have shown promise in automating specific stages of the analog design flow, the development of holistic, end-to-end frameworks that integrate these stages and iteratively refine layouts using post-layout, parasitic-aware performance feedback is still in its early stages. Furthermore, progress in this direction is hindered by the limited availability of open, high-quality datasets tailored to the analog domain, restricting both the benchmarking and the generalizability of ML-based techniques. To address these limitations, we present OSIRIS, a scalable dataset generation pipeline for analog IC design. OSIRIS systematically explores the design space of analog circuits while producing comprehensive performance metrics and metadata, thereby enabling ML-driven research in electronic design automation (EDA). In addition, we release a dataset consisting of 87,100 circuit variations generated with OSIRIS, accompanied by a reinforcement learning (RL)-based baseline method that exploits OSIRIS for analog design optimization.

Figures (14)

• Figure 1: The analog design flow comprises two phases (i) front-end, which translates design requirements into a schematic, (ii) back-end, which generates the corresponding layout. Unlike existing back-end methods that rely on single-pass automation, OSIRIS enables iterative exploration strategies.
• Figure 2: Degrees of freedom explored by OSIRIS. (\ref{['sfig:2_fins']}) a $2$-finger transistor, (\ref{['sfig:4_fins']}) a $4$-finger transistor, and (\ref{['sfig:halo']}) a halo wraps each component, allowing it to move freely within the designated space.
• Figure 3: The OSIRIS pipeline. It takes as inputs a netlist template (TP), a testbench (TB), and pairs of parameters matching transistors (Ps). For each TP, OSIRIS generates M netlists (NL). For each NL, it generates N layout variants (characterized by GDS and QoS files). Therefore, it generates M$\times$N layout variants. It is divided into two stages, (i)Fingers Permutation and (ii)Variants Generation.
• Figure 4: Dataset structure. It contains two directories, netlists and data. The latter is further divided into four subfolders, simulations, metrics, layouts, and metadata.
• Figure 5: RL Variants Generation employs a two-level iterative RL-driven optimization process. It takes as inputs a set of netlists NL and a TB and generates as outputs a set of GDS and QoS. The outer level navigates transistor fingers permutations (stage FinPerm Search), while the inner level explores components movements (stage Spatial Exploration).