Table of Contents
Fetching ...

Quantum Error Correction on Error-mitigated Physical Qubits

Minjun Jeon, Zhenyu Cai

TL;DR

The paper addresses the challenge of achieving practical quantum fault tolerance with limited qubits by proposing a hybrid approach that applies linear quantum error mitigation (QEM) directly to physical qubits before quantum error correction (QEC). It develops a general framework showing that linear QEM methods, including probabilistic error cancellation (PEC) and zero-noise extrapolation (ZNE), can be integrated atop any QEC code without modifying the QEC decoder, and analytically proves that PEC cancels the leading $\mathcal{O}(p^{\lceil d/2\rceil})$ logical-error terms, effectively increasing the code distance by 2. The paper substantiates these claims with simulations on repetition codes and rotated surface codes, demonstrating that a distance-3 code with physical-level PEC can achieve logical-error rates as good as or better than a distance-5 unmitigated code while using 40%–64% fewer qubits. This physical-level QEM approach offers a resource-efficient pathway toward early fault-tolerant architectures, broadening the practical impact of QEC by leveraging existing linear QEM techniques across multiple codes and noise models.

Abstract

We present a general framework for applying linear quantum error mitigation (QEM) techniques directly to physical qubits within a logical qubit to suppress logical errors. By exploiting the linearity of quantum error correction (QEC), we demonstrate that any linear QEM method$\unicode{x2014}$including probabilistic error cancellation (PEC), zero-noise extrapolation (ZNE), and symmetry verification$\unicode{x2014}$can be integrated into the physical layer without requiring modifications to the subsequent QEC decoder. Applying this framework to memory experiments using PEC, we analytically prove and numerically verify that the leading-order contribution to the logical error can be removed, increasing the effective code distance by 2. Our simulations on repetition and rotated surface codes show that a distance-3 code with physical-level PEC achieves logical error rates lower than or similar to a distance-5 unmitigated code while using 40% and 64% fewer qubits, respectively. These results establish physical-level QEM as a widely compatible and resource-efficient strategy for enhancing logical performance in early fault-tolerant architectures.

Quantum Error Correction on Error-mitigated Physical Qubits

TL;DR

The paper addresses the challenge of achieving practical quantum fault tolerance with limited qubits by proposing a hybrid approach that applies linear quantum error mitigation (QEM) directly to physical qubits before quantum error correction (QEC). It develops a general framework showing that linear QEM methods, including probabilistic error cancellation (PEC) and zero-noise extrapolation (ZNE), can be integrated atop any QEC code without modifying the QEC decoder, and analytically proves that PEC cancels the leading logical-error terms, effectively increasing the code distance by 2. The paper substantiates these claims with simulations on repetition codes and rotated surface codes, demonstrating that a distance-3 code with physical-level PEC can achieve logical-error rates as good as or better than a distance-5 unmitigated code while using 40%–64% fewer qubits. This physical-level QEM approach offers a resource-efficient pathway toward early fault-tolerant architectures, broadening the practical impact of QEC by leveraging existing linear QEM techniques across multiple codes and noise models.

Abstract

We present a general framework for applying linear quantum error mitigation (QEM) techniques directly to physical qubits within a logical qubit to suppress logical errors. By exploiting the linearity of quantum error correction (QEC), we demonstrate that any linear QEM methodincluding probabilistic error cancellation (PEC), zero-noise extrapolation (ZNE), and symmetry verificationcan be integrated into the physical layer without requiring modifications to the subsequent QEC decoder. Applying this framework to memory experiments using PEC, we analytically prove and numerically verify that the leading-order contribution to the logical error can be removed, increasing the effective code distance by 2. Our simulations on repetition and rotated surface codes show that a distance-3 code with physical-level PEC achieves logical error rates lower than or similar to a distance-5 unmitigated code while using 40% and 64% fewer qubits, respectively. These results establish physical-level QEM as a widely compatible and resource-efficient strategy for enhancing logical performance in early fault-tolerant architectures.
Paper Structure (29 sections, 66 equations, 11 figures, 2 tables)

This paper contains 29 sections, 66 equations, 11 figures, 2 tables.

Figures (11)

  • Figure 1: Circuit implementation of QEM at the physical level without QEC (without the dashed-boxed $\mathcal{R}$ channel) and with QEC on top (with the dashed-boxed $\mathcal{R}$ channel).
  • Figure 2: Illustration of the distance-$3$ repetition code with bit-flip errors ($p=0.03$): (a) Unmitigated circuit (identity branch) (b) circuit with PEC (superbranch). The first round of stabiliser check here effectively projects the incoming state into the code space (when keeping track of the relevant correction). There are additional weight-$2$ bit-flips sampled from the superbranch. "R" stands for initialisation, "M" stands for measurement. The red boxes stand for noise locations and additional gates inserted by PEC.
  • Figure 3: Logical error rates with and without PEC against physical error rates for (a) repetition code under bit-flip noise (b) rotated surface code under depolarising noise. Note that we are actually plotting the absolute value of the logical error rate for the PEC curves here since the actual value is negative as described in \ref{['sec:negative_log_err']}.
  • Figure 4: Illustration of the distance-$3$ rotated surface code with depolarising errors ($p=0.03$): (a) Unmitigated circuit (identity branch) (b) circuit with PEC (superbranch). There are additional weight-$2$ errors sampled from the superbranch.
  • Figure 5: The sampled (dots) and predicted/fitted (dotted lines) branch-conditioned logical error rates: (a,b) for bit-flip noise and (c,d) for the depolarising noise. The logical error rate of the identity branch, $P^{(0)}_{L}$, was given by its truncated series expression(\ref{['eqn: PI_surface_branch_series']}) with $D_{k}$'s directly obtained from the decoder. The logical error rate of the superbranch was estimated by fitting $s_{1}, \: s_{2}, \: s_{3}$ in its truncated series expression (\ref{['eqn: PS_surface_branch_series']}) on the sampled $P^{(\omega)}_{L}$.
  • ...and 6 more figures