Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures

TL;DR

This work introduces Lifecycle Cost Effectiveness (LCE) to quantify the amortized cost per unit of compute in redundancy-enhanced multi-chiplet architectures. It combines an engineering cost model with reliability-driven lifetime and a lifecycle compute capacity metric, using Monte Carlo yield with Negative Binomial defect clustering and redundancy-aware fault recovery to evaluate economic efficiency. The framework is validated against Chiplet Actuary data and applied to intra- and inter-chiplet redundancy configurations, revealing that coordinated co-optimization across modules, routers, and chiplets yields the best LCE. The findings offer design guidelines for cost-effective chiplet-based AI accelerators and demonstrate the practical impact of lifetime depreciation and redundancy on total cost of ownership.

Abstract

The growing demand for compute-intensive applications has made multi-chiplet architectures a promising alternative to monolithic designs, offering improved scalability and manufacturing flexibility. However, effectively managing the economic effectiveness remains challenging. Existing cost models either overlook the amortization of compute value over a chip's operational lifetime or fail to evaluate how redundancy strategies, which are widely adopted to enhance yield and fault tolerance, impact long-term cost efficiency. This paper presents a comprehensive cost-effectiveness framework for multi-chiplet architectures, introducing a novel Lifecycle Cost Effectiveness (LCE) metric that evaluates amortized compute costs by jointly optimizing manufacturing expenses and operational lifetime. Our approach uniquely integrates: (1) redundancy-aware cost modeling spanning both intra- and inter-chiplet levels, (2) reliability-driven lifetime estimation, and (3) quantitative analysis of how redundancy configurations on overall economic effectiveness. Extensive trade-off and multi-objective optimization studies demonstrate the effectiveness of the model and reveal essential co-optimization strategies between module and chiplet-level redundancy to achieve cost-efficient multi-chiplet architecture designs.

Figures (15)

• Figure 1: Integrated Chip Manufacturing and Operation Lifecycle.
• Figure 2: The configuration optimized for chiplet manufacturing cost can be suboptimal for lifecycle cost-effectiveness, as different chiplet arrangements can affect key factors such as operational lifetime and manufacturing yield differently across the overall multi-chiplet architecture.
• Figure 3: Illustration of chiplet-based architecture and redundancy assumptions. Each subfigure illustrates a model assumption: (a) single-chiplet integration in a 2.5D SCMS architecture; (b) module-level redundancy via additional core-router units; (c) router-level redundancy with $M$:$1$ rerouting; (d) inter-chiplet redundancy through spare chiplet bonding.
• Figure 4: The proposed chiplet yield estimation flow based on Monte Carlo simulation
• Figure 5: Overall Framework of the Cost-effectiveness Model. The framework integrates engineering cost and lifecycle compute capacity models to compute the LCE metric, with architecture configuration parameters (e.g., redundancy strategies) affecting yield, cost, and lifetime compute throughput.