RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version)

TL;DR

RTeAAL Sim reinterprets RTL CPU simulation as sparse tensor algebra, using Extended Einsums (EDGE) and TeAAL’s separation of concerns to decouple computation from binary size. A proof-of-concept FIRRTL-based pipeline demonstrates tensor-cascade kernels with format compression and loop unrolling, achieving performance competitive with Verilator while reducing compilation overhead. The approach preserves RTL-specific optimizations and enables new optimizations through tensor-algebra techniques, offering a scalable path toward hardware-accelerated RTL simulation. This work foregrounds a generalizable framework for applying sparse tensor algebra to RTL workloads and related hardware-design verification tasks.

Abstract

RTL simulation on CPUs remains a persistent bottleneck in hardware design. State-of-the-art simulators embed the circuit directly into the simulation binary, resulting in long compilation times and execution that is fundamentally CPU frontend-bound, with severe instruction-cache pressure. This work proposes RTeAAL Sim, which reformulates RTL simulation as a sparse tensor algebra problem. By representing RTL circuits as tensors and simulation as a sparse tensor algebra kernel, RTeAAL Sim decouples simulation behavior from binary size and makes RTL simulation amenable to well-studied tensor algebra optimizations. We demonstrate that a prototype of our tensor-based simulator, even with a subset of these optimizations, already mitigates the compilation overhead and frontend pressure and achieves performance competitive with the highly optimized Verilator simulator across multiple CPUs and ISAs.

Figures (23)

• Figure 1: Workflow for CPU- and compilation–based RTL simulation. The RTL of a synchronous circuit (left) is lowered onto a dataflow graph (middle) capturing the next-state logic. The simulator then compiles this graph into explicit C++ code (right) to compute and commit register next states each cycle.
• Figure 2: A matrix $A$ and its fibertree representation. The matrix has two ranks, row rank $M$ and column rank $K$. $A_{0,2}$ is an element at point $(0, 2)$ with scalar value $1$. In the fibertree view, rank $M$ contains a single fiber of shape $3$ with occupancy $2$, while rank $K$ contains two fibers with occupancies $1$ and $3$, respectively, both with shape $3$. The leaf payloads correspond to the scalar values stored in the matrix.
• Figure 3: Dot product Einsum and its stepwise breakdown. Example tensors are shown below each action to illustrate values consumed and operations performed at each step.
• Figure 4: Tensor and fibertree notation for illustrating take left ($\leftarrow$) and take right ($\rightarrow$) operators shown in Einsum \ref{['eq:elementmul_coord']}.
• Figure 5: The TeAAL separation of concerns for describing tensor algebra kernels teaal.