CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration

TL;DR

This paper addresses the challenge of efficiently balancing compute and storage in SRAM-CIM accelerators under area constraints. It introduces CIM-Tuner, a hardware-mapping co-design framework built on a matrix abstraction of CIM macros and a generalized accelerator template, combined with fine-grained accelerator-level scheduling and macro-level AF/PF tiling, optimized via simulated annealing. The approach yields substantial gains over prior CIM mapping methods, achieving up to 1.58× higher energy efficiency and 2.11× higher throughput across multiple networks, with additional improvements on state-of-the-art CIM accelerators TranCIM and TP-DCIM under equal area budgets; silicon verification confirms the modeling accuracy, and the tool is open-sourced for community use. Overall, CIM-Tuner provides a universal, scalable pathway to optimize compute-storage balance in SRAM-CIM designs, enabling more energy-efficient and high-throughput DNN accelerators at fixed chip area.

Abstract

As an emerging type of AI computing accelerator, SRAM Computing-In-Memory (CIM) accelerators feature high energy efficiency and throughput. However, various CIM designs and under-explored mapping strategies impede the full exploration of compute and storage balancing in SRAM-CIM accelerator, potentially leading to significant performance degradation. To address this issue, we propose CIM-Tuner, an automatic tool for hardware balancing and optimal mapping strategy under area constraint via hardware-mapping co-exploration. It ensures universality across various CIM designs through a matrix abstraction of CIM macros and a generalized accelerator template. For efficient mapping with different hardware configurations, it employs fine-grained two-level strategies comprising accelerator-level scheduling and macro-level tiling. Compared to prior CIM mapping, CIM-Tuner's extended strategy space achieves 1.58$\times$ higher energy efficiency and 2.11$\times$ higher throughput. Applied to SOTA CIM accelerators with identical area budget, CIM-Tuner also delivers comparable improvements. The simulation accuracy is silicon-verified and CIM-Tuner tool is open-sourced at https://github.com/champloo2878/CIM-Tuner.git.

Figures (10)

• Figure 1: Latency breakdown of matrix multiplication on systolic accelerator. Evaluated using scale-sim scale-sim. Left: varying weight buffer in weight stationary mapping. Right: varying input buffer in input stationary mapping.
• Figure 2: (a) The SCR mechanism in both digital and analog CIM. (b) The latency of matrix multiplication across different hardware proportions and mapping strategies. See evaluation setup in Section IV.
• Figure 3: Overview of CIM-Tuner's hardware-mapping co-exploration.
• Figure 4: Generalized three-stage pipelined CIM accelerator (top) and proposed matrix abstraction of SRAM-CIM macro (bottom).
• Figure 5: Accelerator-level scheduling strategies, IS and OS are short for Input SRAM and Output SRAM, respectively: (a) Non-Reversed (NR) and Reversed (R) spatial scheduling. (b) Input-Priority (IP) and Weight-Priority (WP) temporal scheduling.