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EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization

Wei-Po Hsin, Ren-Hao Deng, Yao-Ting Hsieh, En-Ming Huang, Shih-Hao Hung

TL;DR

EvolVE introduces a model-agnostic evolutionary framework for Verilog generation and PPA optimization by coupling two search strategies, Idea-Guided Refinement (IGR) and Monte Carlo Tree Search (MCTS), with a Structured Testbench Generation (STG) feedback loop. The approach treats HDL design as a state-space search, using dense, phase-based testbenches and dynamic feedback to drive iterative self-correction without heavy fine-tuning. It demonstrates state-of-the-art results on VerilogEval v2 (up to 98.1% pass) and RTLLM v2 (up to 92%), and delivers substantial PPA improvements on industry-scale IC-RTL benchmarks, including up to 66% reduction in the PPA product for Huffman Coding. The work presents Mod-VerilogEval v2 to fix evaluation gaps and IC-RTL to bridge academia and industry, underscoring that evolutionary guidance can enable LLMs to excel in specification-to-RTL generation, targeted optimization, and microarchitectural exploration, even with limited data and compute budgets.

Abstract

Verilog's design cycle is inherently labor-intensive and necessitates extensive domain expertise. Although Large Language Models (LLMs) offer a promising pathway toward automation, their limited training data and intrinsic sequential reasoning fail to capture the strict formal logic and concurrency inherent in hardware systems. To overcome these barriers, we present EvolVE, the first framework to analyze multiple evolution strategies on chip design tasks, revealing that Monte Carlo Tree Search (MCTS) excels at maximizing functional correctness, while Idea-Guided Refinement (IGR) proves superior for optimization. We further leverage Structured Testbench Generation (STG) to accelerate the evolutionary process. To address the lack of complex optimization benchmarks, we introduce IC-RTL, targeting industry-scale problems derived from the National Integrated Circuit Contest. Evaluations establish EvolVE as the new state-of-the-art, achieving 98.1% on VerilogEval v2 and 92% on RTLLM v2. Furthermore, on the industry-scale IC-RTL suite, our framework surpasses reference implementations authored by contest participants, reducing the Power, Performance, Area (PPA) product by up to 66% in Huffman Coding and 17% in the geometric mean across all problems. The source code of the IC-RTL benchmark is available at https://github.com/weiber2002/ICRTL.

EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization

TL;DR

EvolVE introduces a model-agnostic evolutionary framework for Verilog generation and PPA optimization by coupling two search strategies, Idea-Guided Refinement (IGR) and Monte Carlo Tree Search (MCTS), with a Structured Testbench Generation (STG) feedback loop. The approach treats HDL design as a state-space search, using dense, phase-based testbenches and dynamic feedback to drive iterative self-correction without heavy fine-tuning. It demonstrates state-of-the-art results on VerilogEval v2 (up to 98.1% pass) and RTLLM v2 (up to 92%), and delivers substantial PPA improvements on industry-scale IC-RTL benchmarks, including up to 66% reduction in the PPA product for Huffman Coding. The work presents Mod-VerilogEval v2 to fix evaluation gaps and IC-RTL to bridge academia and industry, underscoring that evolutionary guidance can enable LLMs to excel in specification-to-RTL generation, targeted optimization, and microarchitectural exploration, even with limited data and compute budgets.

Abstract

Verilog's design cycle is inherently labor-intensive and necessitates extensive domain expertise. Although Large Language Models (LLMs) offer a promising pathway toward automation, their limited training data and intrinsic sequential reasoning fail to capture the strict formal logic and concurrency inherent in hardware systems. To overcome these barriers, we present EvolVE, the first framework to analyze multiple evolution strategies on chip design tasks, revealing that Monte Carlo Tree Search (MCTS) excels at maximizing functional correctness, while Idea-Guided Refinement (IGR) proves superior for optimization. We further leverage Structured Testbench Generation (STG) to accelerate the evolutionary process. To address the lack of complex optimization benchmarks, we introduce IC-RTL, targeting industry-scale problems derived from the National Integrated Circuit Contest. Evaluations establish EvolVE as the new state-of-the-art, achieving 98.1% on VerilogEval v2 and 92% on RTLLM v2. Furthermore, on the industry-scale IC-RTL suite, our framework surpasses reference implementations authored by contest participants, reducing the Power, Performance, Area (PPA) product by up to 66% in Huffman Coding and 17% in the geometric mean across all problems. The source code of the IC-RTL benchmark is available at https://github.com/weiber2002/ICRTL.
Paper Structure (37 sections, 5 equations, 6 figures, 8 tables, 1 algorithm)

This paper contains 37 sections, 5 equations, 6 figures, 8 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Hardware Description Languages
  4. LLMs for Code Generation
  5. LLMs for Verilog Generation
  6. Domain-Specific Fine-Tuning.
  7. Agentic and Search-Based Frameworks.
  8. The Complexity Gap of Benchmarking PPA
  9. Current Limitations and Our Approach
  10. Methodology
  11. Problem Definition
  12. Frameworks
  13. Idea-Guided Refinement (IGR).
  14. Monte Carlo Tree Search (MCTS).
  15. Evaluation Mechanism: Structured Testbench Generation
  16. ...and 22 more sections

Figures (6)

  • Figure 1: Overview of the EvolVE search framework.
  • Figure 2: Comparative procedural flow for IGR and MCTS.
  • Figure 3: Performance scaling of MCTS across benchmarks and models.
  • Figure 4: Convergence efficiency gains from STG on Mod-VerilogEval v2 benchmark.
  • Figure 5: PPA improvements relative to human baselines on the IC-RTL benchmark.
  • ...and 1 more figures