Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

TL;DR

This work tackles the slow convergence and high memory demands of traditional SA when solving large combinatorial optimization problems. It introduces hardware-aware SSA (HA-SSA), a memory-efficient adaptation with integer, hardware-friendly pseudoinverse temperature control that preserves solution quality while reducing spin-state storage. The authors implement HA-SSA on a Xilinx Kintex-7 FPGA, demonstrating up to 6× memory savings and up to 114× faster convergence than SA on MAX-CUT benchmarks, and achieving best-known solutions with substantially faster annealing times than a competitive FPGA-based method. The approach offers a scalable path to rapid, high-quality optimization in hardware and shows potential for broader applicability to problems with integer weights and dense or sparse Ising models.

Abstract

Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the problem grows. Recently, a stochastic simulated annealing (SSA) algorithm that converges faster than conventional SA has been reported. In this paper, we present a hardware-aware SSA (HA- SSA) algorithm for memory-efficient FPGA implementations. HA-SSA can reduce the memory usage of storing intermediate results while maintaining the computing speed of SSA. For evaluation purposes, the proposed algorithm is compared with the conventional SSA and SA approaches on maximum cut combinatorial optimization problems. HA-SSA achieves a convergence speed that is up to 114-times faster than that of the conventional SA algorithm depending on the maximum cut problem selected from the G-set which is a dataset of the maximum cut problems. HA-SSA is implemented on a field-programmable gate array (FPGA) (Xilinx Kintex-7), and it achieves up to 6-times the memory efficiency of conventional SSA while maintaining high solution quality for optimization problems.

Figures (12)

• Figure 1: The structure of the Ising model and its energy landscape. (a) The configuration of the Ising model for SA. (b) The transition of the spin state and the convergence of the Ising energy.
• Figure 2: A finite state machine (FSM) for $\mathrm{Itanh}$ function.
• Figure 3: The pseudoinverse temperature $I_0$ of the proposed SSA algorithm, and the landscape of the Ising energy.
• Figure 4: The MAX-CUT problem. (a) An example of a MAX-CUT problem. (b) Incorrect solution. (c) Correct solution.
• Figure 5: Block diagram of the spin-gate circuit.