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Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores

Luca Colagrande, Luca Benini

TL;DR

The paper tackles the challenge of delivering efficient dual-issue execution on lightweight, in-order RISC-V cores under tight energy and area constraints. It introduces COPIFTv2, a streamlined extension that uses two lightweight inter-thread queues (I2F and F2I) and a custom CSR to enable direct, fine-grained communication between integer and FP threads, eliminating memory-based data transfers and complex software-pipelining. Empirical results show COPIFTv2 achieving up to $1.81$ IPC, up to $1.49$× peak speedup and $1.47$× peak energy efficiency gains over COPIFT (with a geomean of $1.19$× and $1.21$×, respectively), while maintaining similar power and negligible area overhead, and enabling a more programmable workflow. The work demonstrates that modest architectural support via lightweight queues can unlock substantial dual-issue performance on lightweight cores without sacrificing energy efficiency, and the implementation is open-source and reproducible.

Abstract

Large-scale ML accelerators rely on large numbers of PEs, imposing strict bounds on the area and energy budget of each PE. Prior work demonstrates that limited dual-issue capabilities can be efficiently integrated into a lightweight in-order open-source RISC-V core (Snitch), with a geomean IPC boost of 1.6x and a geomean energy efficiency gain of 1.3x, obtained by concurrently executing integer and FP instructions. Unfortunately, this required a complex and error-prone low level programming model (COPIFT). We introduce COPIFTv2 which augments Snitch with lightweight queues enabling direct, fine-grained communication and synchronization between integer and FP threads. By eliminating the tiling and software pipelining steps of COPIFT, we can remove much of its complexity and software overheads. As a result, COPIFTv2 achieves up to a 1.49x speedup and a 1.47x energy-efficiency gain over COPIFT, and a peak IPC of 1.81. Overall, COPIFTv2 significantly enhances the efficiency and programmability of dual-issue execution on lightweight cores. Our implementation is fully open source and performance experiments are reproducible using free software.

Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores

TL;DR

The paper tackles the challenge of delivering efficient dual-issue execution on lightweight, in-order RISC-V cores under tight energy and area constraints. It introduces COPIFTv2, a streamlined extension that uses two lightweight inter-thread queues (I2F and F2I) and a custom CSR to enable direct, fine-grained communication between integer and FP threads, eliminating memory-based data transfers and complex software-pipelining. Empirical results show COPIFTv2 achieving up to IPC, up to × peak speedup and × peak energy efficiency gains over COPIFT (with a geomean of × and ×, respectively), while maintaining similar power and negligible area overhead, and enabling a more programmable workflow. The work demonstrates that modest architectural support via lightweight queues can unlock substantial dual-issue performance on lightweight cores without sacrificing energy efficiency, and the implementation is open-source and reproducible.

Abstract

Large-scale ML accelerators rely on large numbers of PEs, imposing strict bounds on the area and energy budget of each PE. Prior work demonstrates that limited dual-issue capabilities can be efficiently integrated into a lightweight in-order open-source RISC-V core (Snitch), with a geomean IPC boost of 1.6x and a geomean energy efficiency gain of 1.3x, obtained by concurrently executing integer and FP instructions. Unfortunately, this required a complex and error-prone low level programming model (COPIFT). We introduce COPIFTv2 which augments Snitch with lightweight queues enabling direct, fine-grained communication and synchronization between integer and FP threads. By eliminating the tiling and software pipelining steps of COPIFT, we can remove much of its complexity and software overheads. As a result, COPIFTv2 achieves up to a 1.49x speedup and a 1.47x energy-efficiency gain over COPIFT, and a peak IPC of 1.81. Overall, COPIFTv2 significantly enhances the efficiency and programmability of dual-issue execution on lightweight cores. Our implementation is fully open source and performance experiments are reproducible using free software.
Paper Structure (4 sections, 3 figures)

This paper contains 4 sections, 3 figures.

Table of Contents

  1. Introduction
  2. Implementation
  3. Results
  4. Conclusion

Figures (3)

  • Figure 1: (a) Snitch architecture; (b) Integer and FP phases of the exp kernel; (c) COPIFT schedule and lifetime of buffers.
  • Figure 2: \ref{['step:queues']} transform applied to register- (top) and memory-carried (bottom) dependencies: (left) original code; (center) COPIFTv2 transform; (right) equivalent COPIFT transform.
  • Figure 3: (a, b) Comparison of baseline, COPIFT and COPIFTv2. (c) Speedup and energy savings of COPIFTv2 over COPIFT.