Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency

Sonu Kumar, Lavanya Vinnakota, Mukul Lokhande, Santosh Kumar Vishvakarma, Adam Teman

TL;DR

This work tackles the challenge of edge-AI efficiency under tight hardware and energy constraints by proposing SPADE, a regime-aware, multi-precision SIMD Posit MAC that unifies Posit-8/16/32 execution within a single datapath. The design reuses Posit-specific submodules (LOD, complementor, shifter, multiplier) across precisions via hierarchical lane fusion, achieving precision adaptability with minimal overhead. RTL/FPGA validation demonstrates substantial resource savings and correct Posit behavior, while ASIC synthesis across multiple nodes shows high frequency and low power, with DNN benchmarks maintaining iso-accuracy relative to floating-point baselines. Overall, SPADE offers high throughput, compact area, and energy efficiency for edge accelerators, enabling mixed-precision Posit-enabled inference and paving the way for transprecision workloads at the edge.

Abstract

The growing demand for edge-AI systems requires arithmetic units that balance numerical precision, energy efficiency, and compact hardware while supporting diverse formats. Posit arithmetic offers advantages over floating- and fixed-point representations through its tapered precision, wide dynamic range, and improved numerical robustness. This work presents SPADE, a unified multi-precision SIMD Posit-based multiplyaccumulate (MAC) architecture supporting Posit (8,0), Posit (16,1), and Posit (32,2) within a single framework. Unlike prior single-precision or floating/fixed-point SIMD MACs, SPADE introduces a regime-aware, lane-fused SIMD Posit datapath that hierarchically reuses Posit-specific submodules (LOD, complementor, shifter, and multiplier) across 8/16/32-bit precisions without datapath replication. FPGA implementation on a Xilinx Virtex-7 shows 45.13% LUT and 80% slice reduction for Posit (8,0), and up to 28.44% and 17.47% improvement for Posit (16,1) and Posit (32,2) over prior work, with only 6.9% LUT and 14.9% register overhead for multi-precision support. ASIC results across TSMC nodes achieve 1.38 GHz at 6.1 mW (28 nm). Evaluation on MNIST, CIFAR-10/100, and alphabet datasets confirms competitive inference accuracy.

SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency

TL;DR

This work tackles the challenge of edge-AI efficiency under tight hardware and energy constraints by proposing SPADE, a regime-aware, multi-precision SIMD Posit MAC that unifies Posit-8/16/32 execution within a single datapath. The design reuses Posit-specific submodules (LOD, complementor, shifter, multiplier) across precisions via hierarchical lane fusion, achieving precision adaptability with minimal overhead. RTL/FPGA validation demonstrates substantial resource savings and correct Posit behavior, while ASIC synthesis across multiple nodes shows high frequency and low power, with DNN benchmarks maintaining iso-accuracy relative to floating-point baselines. Overall, SPADE offers high throughput, compact area, and energy efficiency for edge accelerators, enabling mixed-precision Posit-enabled inference and paving the way for transprecision workloads at the edge.

Abstract

The growing demand for edge-AI systems requires arithmetic units that balance numerical precision, energy efficiency, and compact hardware while supporting diverse formats. Posit arithmetic offers advantages over floating- and fixed-point representations through its tapered precision, wide dynamic range, and improved numerical robustness. This work presents SPADE, a unified multi-precision SIMD Posit-based multiplyaccumulate (MAC) architecture supporting Posit (8,0), Posit (16,1), and Posit (32,2) within a single framework. Unlike prior single-precision or floating/fixed-point SIMD MACs, SPADE introduces a regime-aware, lane-fused SIMD Posit datapath that hierarchically reuses Posit-specific submodules (LOD, complementor, shifter, and multiplier) across 8/16/32-bit precisions without datapath replication. FPGA implementation on a Xilinx Virtex-7 shows 45.13% LUT and 80% slice reduction for Posit (8,0), and up to 28.44% and 17.47% improvement for Posit (16,1) and Posit (32,2) over prior work, with only 6.9% LUT and 14.9% register overhead for multi-precision support. ASIC results across TSMC nodes achieve 1.38 GHz at 6.1 mW (28 nm). Evaluation on MNIST, CIFAR-10/100, and alphabet datasets confirms competitive inference accuracy.
Paper Structure (6 sections, 4 figures, 3 tables)

This paper contains 6 sections, 4 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Proposed Work
  3. Background & Motivation
  4. SPADE MAC Engine
  5. Methodology and Evaluation
  6. Conclusion & Future Work

Figures (4)

  • Figure 1: Proposed regime-aware SIMD Posit-8/16/32 MAC datapath illustrating hierarchical lane fusion and shared Posit-specific submodules.
  • Figure 2: Detailed internal circuitry showcasing SIMD configurable circuit blocks: (a) Leading-One Detector, (b) complementor in the accumulation stage, (c) multi-stage logarithmic barrel shifter, and multiplier in (d) 8-bit, (e) 16-bit and (f) 32-bit partition mode.
  • Figure 3: Detailed micro-architecture for SIMD Posit compute engine based systolic array architecture, Cheshire interface (CVA6)Cheshire, control unit and memory banks.
  • Figure 4: Comparative application accuracy for image classification, against prior works.