Inverter-Based Differential Amplifiers With Back-Gate Feedback Linearization

TL;DR

Problem: RF receivers are often limited by linearity rather than noise. Approach: integrate back-gate feedback with inverter-based differential amplifiers in FD-SOI to achieve a closed-loop gain largely set by process capacitances and to enhance IP3, validated by analysis and 22FD-SOI simulations. Contributions: derive $A_v \approx 1/\chi$, show no extra noise from feedback, quantify IP3 improvements up to hundreds of times with longer channels, and demonstrate improved CMRR with dual CMFB; provide design insights for biasing and common-mode rejection. Significance: offers a practical, power-efficient path to higher RF linearity in crowded spectra using FD-SOI back-gate linearization for differential amplifier cores.

Abstract

Feeding the common-source amplifier output to the back-gate terminal in fully depleted silicon on insulator (FD-SOI) technology exploits the linearizing effect of negative feedback. Analysis and simulation results in 22 nm FD-SOI show that back-gate feedback sets the overall gain approximately independent of the load, contributes no additional noise, and improves linearity by the back-gate voltage gain. Third-order intercept point (IP3) enhancement is at least $60\times$ compared to without feedback in inverter-based, or complementary common-source, differential amplifiers.

Figures (8)

• Figure 1: Intrinsic gain stage (a) with back-gate feedback and (b) block diagram representation.
• Figure 2: Complementary common-source stage (a) in open loop and (b) with back-gate feedback.
• Figure 3: Inverter large-signal behavior in open loop and with back-gate feedback in FD-SOI technology.
• Figure 4: (a) Single and (b) dual common-mode feedback (SCMFB and DCMFB, respectively) differential amplifiers.
• Figure 5: Calculated and simulated differential-mode gain.