Real-Time Evaluation of an Ultra-Tight GNSS/INS Integration Based on Adaptive PLL Bandwidth

TL;DR

This work tackles robust GNSS positioning in challenging environments by fusing GNSS with an INS in an ultra-tight, vector-tracking framework. The authors propose UT-ALFA, a decentralized VDFLL variant that preserves a conventional FLL-assisted PLL while adaptively tuning the PLL bandwidth based on the Doppler-rate $\dot{f}_d$ supplied by an EKF-driven navigation filter. By delivering Doppler-rate updates to the loop rather than propagating full EKF state back to NCOs, UT-ALFA reduces data-synchronization complexity and hardware burden, achieving near VDFLL performance with simpler FPGA implementation. The approach demonstrates stable pseudorange estimates and Doppler RMSE better than $0.1$ Hz in degraded $\mathrm{C/N_0}$ scenarios and is validated on a Xilinx ZCU102 with Matlab-in-the-loop and real-data experiments, indicating practical impact for real-time autonomous systems with limited resources.

Abstract

In this contribution, we propose a GNSS/INS ultra-tight coupling in which the GNSS receiver architecture is based on a vector tracking loop type architecture. In the proposed approach, the phase lock loop bandwidth is adapted according to the inertial navigation system information. The latter has the advantage to be easily implementable on a System-on-Chip component such as an FPGA (Field-Programmable Gate Arrays), and can be implemented with minor modifications on an existing GNSS receiver platform. Moreover, compared to classical vector-based solutions, the proposed architecture decodes the navigation message in the loop, without the need to run scalar loops in parallel or having to store pre-downloaded ephemeris data. This architecture therefore does not increase the area occupied on the FPGA and does not use additional resources for storage. The proposed GNSS receiver architecture uses GPS L1/C and Galileo E1 signals and is composed of one acquisition module and 16 tracking channels (8 GPS and 8 Galileo) which are implemented within a FPGA (Zynq-Ultrascale).

Figures (10)

• Figure 1: Ultra-tightly coupled vector delay and frequency lock loop architecture for one tracking channel.
• Figure 2: Ultra-tightly coupled adaptive loop filter architecture (UT-ALFA) for one tracking channel.
• Figure 3: UT-ALFA loop filter for one channel: the FLL-assist from the classical loop filter has been replaced by the Doppler frequency rate.
• Figure 4: ISAE-SUPAERO UT-ALFA architecture on Zynq.
• Figure 5: Simulated trajectory visualized with Google Earth.